upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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124 lines
4.1 KiB
124 lines
4.1 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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/* image version */
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IMAGE_VERSION 2
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#define __ASSEMBLY__
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#include <config.h>
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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#if defined(CONFIG_TQMA6X_MMC_BOOT)
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BOOT_FROM sd
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#elif defined(CONFIG_TQMA6X_SPI_BOOT)
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BOOT_FROM spi
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#endif
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#include "asm/arch/mx6-ddr.h"
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#include "asm/arch/iomux.h"
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#include "asm/arch/crm_regs.h"
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/* TQMa6S DDR config Rev. 0100B */
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/* IOMUX configuration */
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DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
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DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
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DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008000
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DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
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DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
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DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
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DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
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DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
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DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
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DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
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DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
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DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
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DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
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DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
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DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
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DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000
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DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000
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DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000
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DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000
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DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
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DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B4DS, 0x00000000
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DATA 4, MX6_IOM_GRP_B5DS, 0x00000000
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DATA 4, MX6_IOM_GRP_B6DS, 0x00000000
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DATA 4, MX6_IOM_GRP_B7DS, 0x00000000
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DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
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DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
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DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
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DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
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DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000
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DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000
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DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000
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DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000
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/* memory interface calibration values */
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DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
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DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380000
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DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0014000E
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DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00120014
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DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00000000
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DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00000000
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DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x0240023C
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DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0228022C
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DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x00000000
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DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x00000000
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DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4A4A4E4A
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DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x00000000
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DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36362A32
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DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x00000000
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DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x00000000
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DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x00000000
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DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x00000000
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DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x00000000
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DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
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DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000000
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/* configure memory interface */
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DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
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DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
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DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333
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DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63
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DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
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DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
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DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
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DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
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DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
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DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
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DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
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DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
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DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222
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DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
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DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D
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DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
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#include "clocks.cfg"
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