upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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68 lines
1.3 KiB
68 lines
1.3 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013-2014, 2018 Synopsys, Inc. All rights reserved.
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*/
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#include <common.h>
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#include <asm/arcregs.h>
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#include <asm/cache.h>
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DECLARE_GLOBAL_DATA_PTR;
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int arch_cpu_init(void)
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{
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timer_init();
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gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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cache_init();
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return 0;
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}
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int arch_early_init_r(void)
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{
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gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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/* This is a dummy function on arc */
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int dram_init(void)
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{
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return 0;
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}
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#ifdef CONFIG_DISPLAY_CPUINFO
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const char *decode_identity(void)
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{
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int arcver = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
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switch (arcver) {
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/* ARCompact cores */
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case 0x32: return "ARC 700 v4.4-4.5";
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case 0x33: return "ARC 700 v4.6-v4.9";
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case 0x34: return "ARC 700 v4.10";
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case 0x35: return "ARC 700 v4.11";
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/* ARCv2 cores */
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case 0x41: return "ARC EM v1.1a";
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case 0x42: return "ARC EM v3.0";
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case 0x43: return "ARC EM v4.0";
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case 0x50: return "ARC HS v1.0";
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case 0x51: return "ARC EM v2.0";
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case 0x52: return "ARC EM v2.1";
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case 0x53: return "ARC HS v3.0";
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case 0x54: return "ARC HS v4.0";
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default: return "Unknown ARC core";
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}
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}
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__weak int print_cpuinfo(void)
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{
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printf("CPU: %s\n", decode_identity());
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return 0;
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}
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#endif /* CONFIG_DISPLAY_CPUINFO */
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