upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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111 lines
2.5 KiB
111 lines
2.5 KiB
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* FSL USB HOST xHCI Controller
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*
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* Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <usb.h>
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#include <asm-generic/errno.h>
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#include <linux/compat.h>
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#include <linux/usb/xhci-fsl.h>
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#include <linux/usb/dwc3.h>
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#include "xhci.h"
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/* Declare global data pointer */
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DECLARE_GLOBAL_DATA_PTR;
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static struct fsl_xhci fsl_xhci;
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unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR;
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__weak int __board_usb_init(int index, enum usb_init_type init)
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{
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return 0;
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}
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void usb_phy_reset(struct dwc3 *dwc3_reg)
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{
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/* Assert USB3 PHY reset */
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setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
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/* Assert USB2 PHY reset */
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setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
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mdelay(200);
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/* Clear USB3 PHY reset */
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clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
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/* Clear USB2 PHY reset */
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clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
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}
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static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
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{
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int ret = 0;
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ret = dwc3_core_init(fsl_xhci->dwc3_reg);
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if (ret) {
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debug("%s:failed to initialize core\n", __func__);
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return ret;
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}
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/* We are hard-coding DWC3 core to Host Mode */
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dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
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/* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
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dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
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return ret;
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}
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static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
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{
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/*
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* Currently fsl socs do not support PHY shutdown from
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* sw. But this support may be added in future socs.
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*/
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return 0;
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}
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int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
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{
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struct fsl_xhci *ctx = &fsl_xhci;
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int ret = 0;
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ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
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ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
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ret = board_usb_init(index, USB_INIT_HOST);
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if (ret != 0) {
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puts("Failed to initialize board for USB\n");
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return ret;
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}
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ret = fsl_xhci_core_init(ctx);
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if (ret < 0) {
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puts("Failed to initialize xhci\n");
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return ret;
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}
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*hccr = (struct xhci_hccr *)ctx->hcd;
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*hcor = (struct xhci_hcor *)((uintptr_t) *hccr
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+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
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debug("fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n",
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(uintptr_t)*hccr, (uintptr_t)*hcor,
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(uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
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return ret;
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}
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void xhci_hcd_stop(int index)
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{
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struct fsl_xhci *ctx = &fsl_xhci;
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fsl_xhci_core_exit(ctx);
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}
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