upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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139 lines
3.9 KiB
139 lines
3.9 KiB
/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/mx31-regs.h>
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#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
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/* General purpose timers registers */
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#define GPTCR __REG(TIMER_BASE) /* Control register */
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#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */
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#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */
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#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */
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/* General purpose timers bitfields */
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#define GPTCR_SWR (1 << 15) /* Software reset */
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#define GPTCR_FRR (1 << 9) /* Freerun / restart */
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#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
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#define GPTCR_TEN 1 /* Timer enable */
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/* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */
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#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION
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/* ~0.4% error - measured with stop-watch on 100s boot-delay */
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#define TICK_TO_TIME(t) ((t) * CONFIG_SYS_HZ / CONFIG_MX31_CLK32)
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#define TIME_TO_TICK(t) ((unsigned long long)(t) * CONFIG_MX31_CLK32 / CONFIG_SYS_HZ)
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#define US_TO_TICK(t) (((unsigned long long)(t) * CONFIG_MX31_CLK32 + \
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999999) / 1000000)
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#else
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/* ~2% error */
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#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
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#define US_PER_TICK (1000000 / CONFIG_MX31_CLK32)
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#define TICK_TO_TIME(t) ((t) / TICK_PER_TIME)
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#define TIME_TO_TICK(t) ((unsigned long long)(t) * TICK_PER_TIME)
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#define US_TO_TICK(t) (((t) + US_PER_TICK - 1) / US_PER_TICK)
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#endif
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static ulong timestamp;
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static ulong lastinc;
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/* nothing really to do with interrupts, just starts up a counter. */
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/* The 32768Hz 32-bit timer overruns in 131072 seconds */
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int interrupt_init (void)
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{
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int i;
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/* setup GP Timer 1 */
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GPTCR = GPTCR_SWR;
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for (i = 0; i < 100; i++)
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GPTCR = 0; /* We have no udelay by now */
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GPTPR = 0; /* 32Khz */
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/* Freerun Mode, PERCLK1 input */
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GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
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return 0;
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}
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void reset_timer_masked (void)
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{
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/* reset time */
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lastinc = GPTCNT; /* capture current incrementer value time */
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timestamp = 0; /* start "advancing" time stamp from 0 */
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}
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void reset_timer(void)
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{
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reset_timer_masked();
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}
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unsigned long long get_ticks (void)
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{
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ulong now = GPTCNT; /* current tick value */
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if (now >= lastinc) /* normal mode (non roll) */
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/* move stamp forward with absolut diff ticks */
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timestamp += (now - lastinc);
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else /* we have rollover of incrementer */
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timestamp += (0xFFFFFFFF - lastinc) + now;
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lastinc = now;
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return timestamp;
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}
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ulong get_timer_masked (void)
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{
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/*
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* get_ticks() returns a long long (64 bit), it wraps in
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* 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
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* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
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* 5 * 10^6 days - long enough.
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*/
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return TICK_TO_TIME(get_ticks());
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}
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ulong get_timer (ulong base)
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{
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return get_timer_masked () - base;
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}
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void set_timer (ulong t)
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{
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timestamp = TIME_TO_TICK(t);
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}
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/* delay x useconds AND perserve advance timstamp value */
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void udelay (unsigned long usec)
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{
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unsigned long long tmp;
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ulong tmo;
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tmo = US_TO_TICK(usec);
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tmp = get_ticks() + tmo; /* get current timestamp */
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while (get_ticks() < tmp) /* loop till event */
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/*NOP*/;
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}
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void reset_cpu (ulong addr)
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{
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__REG16(WDOG_BASE) = 4;
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}
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