upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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94 lines
2.4 KiB
94 lines
2.4 KiB
/*
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* (C) Copyright 2009
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* Ryan Chen, ST Micoelectronics, ryan.chen@st.com.
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <nand.h>
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#include <asm/io.h>
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#include <linux/mtd/fsmc_nand.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/spr_defs.h>
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#include <asm/arch/spr_misc.h>
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#define PLGPIO_SEL_36 0xb3000028
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#define PLGPIO_IO_36 0xb3000038
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static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
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static void spear_phy_reset(void)
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{
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writel(0x10, PLGPIO_IO_36);
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writel(0x10, PLGPIO_SEL_36);
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}
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int board_init(void)
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{
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spear_phy_reset();
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return spear_board_init(MACH_TYPE_SPEAR320);
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}
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/*
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* board_nand_init - Board specific NAND initialization
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* @nand: mtd private chip structure
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*
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* Called by nand_init_chip to initialize the board specific functions
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*/
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void board_nand_init()
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{
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struct misc_regs *const misc_regs_p =
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(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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struct nand_chip *nand = &nand_chip[0];
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#if defined(CONFIG_NAND_FSMC)
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if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
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MISC_SOCCFG30) ||
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((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
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MISC_SOCCFG31)) {
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fsmc_nand_init(nand);
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}
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#endif
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return;
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}
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int board_eth_init(bd_t *bis)
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{
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int ret = 0;
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#if defined(CONFIG_DESIGNWARE_ETH)
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u32 interface = PHY_INTERFACE_MODE_MII;
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if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
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interface) >= 0)
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ret++;
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#endif
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#if defined(CONFIG_MACB)
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if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE,
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CONFIG_MACB0_PHY) >= 0)
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ret++;
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#endif
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return ret;
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}
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