upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support

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Simon Glass 7ac99be6e2 x86: Add an ICH6 pin configuration driver ... Add a driver which sets up the pin configuration on x86 devices with an ICH6 (or later) Platform Controller Hub. The driver is not in the pinctrl uclass due to some oddities of the way x86 devices work: - The GPIO controller is not present in I/O space until it is set up - This is done by writing a register in the PCH - The PCH has a driver which itself uses PCI, another driver - The pinctrl uclass requires that a pinctrl device be available before any other device can be probed It would be possible to work around the limitations by: - Hard-coding the GPIO address rather than reading it from the PCH - Using special x86 PCI access to set the GPIO address in the PCH However it is not clear that this is better, since the pin configuration driver does not actually provide normal pin configuration services - it simply sets up all the pins statically when probed. While this remains the case, it seems better to use a syscon uclass instead. This can be probed whenever it is needed, without any limitations. Also add an 'invert' property to support inverting the input. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>		9 years ago
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efi	…
fsp	…
Makefile	…
acpi_table.c	…
asm-offsets.c	…
bios.c	…
bios.h	…
bios_asm.S	…
bios_interrupts.c	…
bootm.c	…
cmd_boot.c	…
cmd_mtrr.c	…
coreboot_table.c	…
e820.c	…
gcc.c	…
i8254.c	…
i8259.c	…
init_helpers.c	…
interrupts.c	…
lpc-uclass.c	…
mpspec.c	…
mrccache.c	…
northbridge-uclass.c	…
physmem.c	…
pinctrl_ich6.c	…
pirq_routing.c	…
ramtest.c	…
relocate.c	…
sfi.c	…
smbios.c	…
string.c	…
tables.c	…
zimage.c	…