upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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237 lines
8.8 KiB
237 lines
8.8 KiB
/*
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* (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <serial.h>
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#include <linux/compiler.h>
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#define __REG(x) (*((volatile u32 *)(x)))
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#ifndef CONFIG_MXC_UART_BASE
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#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
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#endif
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#define UART_PHYS CONFIG_MXC_UART_BASE
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/* Register definitions */
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#define URXD 0x0 /* Receiver Register */
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#define UTXD 0x40 /* Transmitter Register */
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#define UCR1 0x80 /* Control Register 1 */
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#define UCR2 0x84 /* Control Register 2 */
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#define UCR3 0x88 /* Control Register 3 */
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#define UCR4 0x8c /* Control Register 4 */
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#define UFCR 0x90 /* FIFO Control Register */
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#define USR1 0x94 /* Status Register 1 */
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#define USR2 0x98 /* Status Register 2 */
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#define UESC 0x9c /* Escape Character Register */
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#define UTIM 0xa0 /* Escape Timer Register */
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#define UBIR 0xa4 /* BRM Incremental Register */
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#define UBMR 0xa8 /* BRM Modulator Register */
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#define UBRC 0xac /* Baud Rate Count Register */
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#define UTS 0xb4 /* UART Test Register (mx31) */
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/* UART Control Register Bit Fields.*/
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#define URXD_CHARRDY (1<<15)
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#define URXD_ERR (1<<14)
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#define URXD_OVRRUN (1<<13)
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#define URXD_FRMERR (1<<12)
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#define URXD_BRK (1<<11)
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#define URXD_PRERR (1<<10)
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#define URXD_RX_DATA (0xFF)
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#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
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#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
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#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
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#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
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#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
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#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
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#define UCR1_IREN (1<<7) /* Infrared interface enable */
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#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
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#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
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#define UCR1_SNDBRK (1<<4) /* Send break */
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#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
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#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
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#define UCR1_DOZE (1<<1) /* Doze */
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#define UCR1_UARTEN (1<<0) /* UART enabled */
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#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
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#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
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#define UCR2_CTSC (1<<13) /* CTS pin control */
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#define UCR2_CTS (1<<12) /* Clear to send */
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#define UCR2_ESCEN (1<<11) /* Escape enable */
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#define UCR2_PREN (1<<8) /* Parity enable */
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#define UCR2_PROE (1<<7) /* Parity odd/even */
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#define UCR2_STPB (1<<6) /* Stop */
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#define UCR2_WS (1<<5) /* Word size */
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#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
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#define UCR2_TXEN (1<<2) /* Transmitter enabled */
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#define UCR2_RXEN (1<<1) /* Receiver enabled */
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#define UCR2_SRST (1<<0) /* SW reset */
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#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
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#define UCR3_PARERREN (1<<12) /* Parity enable */
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#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
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#define UCR3_DSR (1<<10) /* Data set ready */
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#define UCR3_DCD (1<<9) /* Data carrier detect */
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#define UCR3_RI (1<<8) /* Ring indicator */
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#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
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#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
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#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
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#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
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#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
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#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
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#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
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#define UCR3_BPEN (1<<0) /* Preset registers enable */
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#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
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#define UCR4_INVR (1<<9) /* Inverted infrared reception */
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#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
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#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
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#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
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#define UCR4_IRSC (1<<5) /* IR special case */
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#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
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#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
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#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
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#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
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#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
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#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
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#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
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#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
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#define USR1_RTSS (1<<14) /* RTS pin status */
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#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
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#define USR1_RTSD (1<<12) /* RTS delta */
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#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
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#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
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#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
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#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
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#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
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#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
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#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
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#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
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#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
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#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
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#define USR2_IDLE (1<<12) /* Idle condition */
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#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
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#define USR2_WAKE (1<<7) /* Wake */
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#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
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#define USR2_TXDC (1<<3) /* Transmitter complete */
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#define USR2_BRCD (1<<2) /* Break condition */
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#define USR2_ORE (1<<1) /* Overrun error */
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#define USR2_RDR (1<<0) /* Recv data ready */
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#define UTS_FRCPERR (1<<13) /* Force parity error */
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#define UTS_LOOP (1<<12) /* Loop tx and rx */
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#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
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#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
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#define UTS_TXFULL (1<<4) /* TxFIFO full */
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#define UTS_RXFULL (1<<3) /* RxFIFO full */
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#define UTS_SOFTRST (1<<0) /* Software reset */
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DECLARE_GLOBAL_DATA_PTR;
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static void mxc_serial_setbrg(void)
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{
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u32 clk = imx_get_uartclk();
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if (!gd->baudrate)
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gd->baudrate = CONFIG_BAUDRATE;
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__REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */
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__REG(UART_PHYS + UBIR) = 0xf;
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__REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
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}
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static int mxc_serial_getc(void)
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{
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while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
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WATCHDOG_RESET();
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return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */
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}
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static void mxc_serial_putc(const char c)
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{
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__REG(UART_PHYS + UTXD) = c;
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/* wait for transmitter to be ready */
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while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
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WATCHDOG_RESET();
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/* If \n, also do \r */
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if (c == '\n')
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serial_putc ('\r');
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}
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/*
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* Test whether a character is in the RX buffer
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*/
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static int mxc_serial_tstc(void)
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{
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/* If receive fifo is empty, return false */
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if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
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return 0;
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return 1;
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}
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/*
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* Initialise the serial port with the given baudrate. The settings
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* are always 8 data bits, no parity, 1 stop bit, no start bits.
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*
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*/
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static int mxc_serial_init(void)
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{
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__REG(UART_PHYS + UCR1) = 0x0;
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__REG(UART_PHYS + UCR2) = 0x0;
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while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
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__REG(UART_PHYS + UCR3) = 0x0704;
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__REG(UART_PHYS + UCR4) = 0x8000;
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__REG(UART_PHYS + UESC) = 0x002b;
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__REG(UART_PHYS + UTIM) = 0x0;
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__REG(UART_PHYS + UTS) = 0x0;
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serial_setbrg();
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__REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
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__REG(UART_PHYS + UCR1) = UCR1_UARTEN;
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return 0;
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}
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static struct serial_device mxc_serial_drv = {
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.name = "mxc_serial",
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.start = mxc_serial_init,
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.stop = NULL,
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.setbrg = mxc_serial_setbrg,
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.putc = mxc_serial_putc,
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.puts = default_serial_puts,
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.getc = mxc_serial_getc,
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.tstc = mxc_serial_tstc,
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};
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void mxc_serial_initialize(void)
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{
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serial_register(&mxc_serial_drv);
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}
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__weak struct serial_device *default_serial_console(void)
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{
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return &mxc_serial_drv;
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}
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