upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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284 lines
6.7 KiB
284 lines
6.7 KiB
/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* (C) Copyright 2009-2015
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* Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
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* esd electronic system design gmbh <www.esd.eu>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/mach-types.h>
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#include <asm/setup.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/at91_matrix.h>
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#include <asm/arch/at91_pio.h>
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#include <asm/arch/clk.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Miscelaneous platform dependent initialisations
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*/
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#ifdef CONFIG_REVISION_TAG
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static int hw_rev = -1; /* hardware revision */
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int get_hw_rev(void)
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{
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if (hw_rev >= 0)
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return hw_rev;
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hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
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hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
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hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
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hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
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if (hw_rev == 15)
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hw_rev = 0;
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return hw_rev;
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}
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#endif /* CONFIG_REVISION_TAG */
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#ifdef CONFIG_CMD_NAND
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static void meesc_nand_hw_init(void)
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{
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unsigned long csa;
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at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
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at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
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/* Enable CS3 */
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csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
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writel(csa, &matrix->csa[0]);
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/* Configure SMC CS3 for NAND/SmartMedia */
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
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AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_DBW_8 |
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AT91_SMC_MODE_TDF_CYCLE(12),
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&smc->cs[3].mode);
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/* Configure RDY/BSY */
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gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
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/* Enable NandFlash */
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gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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}
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#endif /* CONFIG_CMD_NAND */
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#ifdef CONFIG_MACB
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static void meesc_macb_hw_init(void)
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{
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at91_periph_clk_enable(ATMEL_ID_EMAC);
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at91_macb_hw_init();
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}
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#endif
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/*
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* Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
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* controller debugging
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* The ET1100 is located at physical address 0x70000000
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* Its process memory is located at physical address 0x70001000
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*/
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static void meesc_ethercat_hw_init(void)
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{
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at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1;
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/* Configure SMC EBI1_CS0 for EtherCAT */
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writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
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&smc1->cs[0].setup);
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writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
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AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
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&smc1->cs[0].pulse);
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writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
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&smc1->cs[0].cycle);
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/*
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* Configure behavior at external wait signal, byte-select mode, 16 bit
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* data bus width, none data float wait states and TDF optimization
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*/
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
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AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
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AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
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/* Configure RDY/BSY */
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at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
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}
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
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PHYS_SDRAM_SIZE);
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
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#endif
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return rc;
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}
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard(void)
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{
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char str[32];
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u_char hw_type; /* hardware type */
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/* read the "Type" register of the ET1100 controller */
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hw_type = readb(CONFIG_ET1100_BASE);
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switch (hw_type) {
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case 0x11:
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case 0x3F:
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/* ET1100 present, arch number of MEESC-Board */
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gd->bd->bi_arch_number = MACH_TYPE_MEESC;
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puts("Board: CAN-EtherCAT Gateway");
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break;
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case 0xFF:
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/* no ET1100 present, arch number of EtherCAN/2-Board */
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gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
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puts("Board: EtherCAN/2 Gateway");
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/* switch on LED1D */
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at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
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break;
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default:
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/* assume, no ET1100 present, arch number of EtherCAN/2-Board */
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gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
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printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
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puts("Board: EtherCAN/2 Gateway");
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break;
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}
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if (getenv_f("serial#", str, sizeof(str)) > 0) {
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puts(", serial# ");
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puts(str);
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}
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#ifdef CONFIG_REVISION_TAG
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printf("\nHardware-revision: 1.%d\n", get_hw_rev());
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#endif
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printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
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return 0;
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}
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#endif /* CONFIG_DISPLAY_BOARDINFO */
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#ifdef CONFIG_SERIAL_TAG
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void get_board_serial(struct tag_serialnr *serialnr)
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{
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char *str;
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char *serial = getenv("serial#");
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if (serial) {
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str = strchr(serial, '_');
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if (str && (strlen(str) >= 4)) {
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serialnr->high = (*(str + 1) << 8) | *(str + 2);
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serialnr->low = simple_strtoul(str + 3, NULL, 16);
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}
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} else {
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serialnr->high = 0;
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serialnr->low = 0;
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}
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}
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#endif
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#ifdef CONFIG_REVISION_TAG
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u32 get_board_rev(void)
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{
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return hw_rev | 0x100;
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}
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#endif
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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char *str;
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char buf[32];
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at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
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/*
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* Normally the processor clock has a divisor of 2.
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* In some cases this this needs to be set to 4.
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* Check the user has set environment mdiv to 4 to change the divisor.
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*/
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if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
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writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
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AT91SAM9_PMC_MDIV_4, &pmc->mckr);
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at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
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serial_setbrg();
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/* Notify the user that the clock is not default */
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printf("Setting master clock to %s MHz\n",
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strmhz(buf, get_mck_clk_rate()));
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}
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return 0;
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}
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#endif /* CONFIG_MISC_INIT_R */
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int board_early_init_f(void)
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{
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at91_periph_clk_enable(ATMEL_ID_PIOA);
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at91_periph_clk_enable(ATMEL_ID_PIOB);
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at91_periph_clk_enable(ATMEL_ID_PIOCDE);
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at91_periph_clk_enable(ATMEL_ID_UHP);
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at91_seriald_hw_init();
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return 0;
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}
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int board_init(void)
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{
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/* initialize ET1100 Controller */
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meesc_ethercat_hw_init();
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_CMD_NAND
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meesc_nand_hw_init();
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#endif
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#ifdef CONFIG_HAS_DATAFLASH
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at91_spi0_hw_init(1 << 0);
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#endif
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#ifdef CONFIG_MACB
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meesc_macb_hw_init();
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#endif
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#ifdef CONFIG_AT91_CAN
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at91_can_hw_init();
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#endif
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#ifdef CONFIG_USB_OHCI_NEW
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at91_uhp_hw_init();
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#endif
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return 0;
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}
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