upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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513 lines
9.6 KiB
513 lines
9.6 KiB
/*
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* (C) Copyright 2004
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* DAVE Srl
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* http://www.dave-tech.it
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* http://www.wawnet.biz
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* mailto:info@wawnet.biz
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* S3C44B0 CPU specific code
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/hardware.h>
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static void s3c44b0_flush_cache(void)
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{
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volatile int i;
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/* flush cycle */
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for(i=0x10002000;i<0x10004800;i+=16)
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{
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*((int *)i)=0x0;
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}
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}
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int cpu_init (void)
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{
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icache_enable();
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return 0;
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}
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int cleanup_before_linux (void)
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{
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/*
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cache memory should be enabled before calling
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Linux to make the kernel uncompression faster
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*/
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icache_enable();
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disable_interrupts ();
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return 0;
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}
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void reset_cpu (ulong addr)
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{
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/*
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reset the cpu using watchdog
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*/
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/* Disable the watchdog.*/
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WTCON&=~(1<<5);
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/* set the timeout value to a short time... */
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WTCNT = 0x1;
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/* Enable the watchdog. */
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WTCON|=1;
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WTCON|=(1<<5);
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while(1) {
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/*NOP*/
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}
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}
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int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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disable_interrupts ();
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reset_cpu (0);
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/*NOTREACHED*/
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return (0);
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}
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void icache_enable (void)
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{
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ulong reg;
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s3c44b0_flush_cache();
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/*
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Init cache
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Non-cacheable area (everything outside RAM)
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0x0000:0000 - 0x0C00:0000
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*/
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NCACHBE0 = 0xC0000000;
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NCACHBE1 = 0x00000000;
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/*
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Enable chache
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*/
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reg = SYSCFG;
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reg |= 0x00000006; /* 8kB */
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SYSCFG = reg;
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}
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void icache_disable (void)
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{
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ulong reg;
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reg = SYSCFG;
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reg &= ~0x00000006; /* 8kB */
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SYSCFG = reg;
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}
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int icache_status (void)
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{
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return 0;
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}
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void dcache_enable (void)
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{
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icache_enable();
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}
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void dcache_disable (void)
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{
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icache_disable();
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}
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int dcache_status (void)
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{
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return dcache_status();
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}
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/*
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RTC stuff
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*/
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#include <rtc.h>
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#ifndef BCD2HEX
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#define BCD2HEX(n) ((n>>4)*10+(n&0x0f))
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#endif
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#ifndef HEX2BCD
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#define HEX2BCD(x) ((((x) / 10) << 4) + (x) % 10)
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#endif
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int rtc_get (struct rtc_time* tm)
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{
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RTCCON |= 1;
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tm->tm_year = BCD2HEX(BCDYEAR);
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tm->tm_mon = BCD2HEX(BCDMON);
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tm->tm_wday = BCD2HEX(BCDDATE);
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tm->tm_mday = BCD2HEX(BCDDAY);
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tm->tm_hour = BCD2HEX(BCDHOUR);
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tm->tm_min = BCD2HEX(BCDMIN);
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tm->tm_sec = BCD2HEX(BCDSEC);
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if (tm->tm_sec==0) {
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/* we have to re-read the rtc data because of the "one second deviation" problem */
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/* see RTC datasheet for more info about it */
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tm->tm_year = BCD2HEX(BCDYEAR);
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tm->tm_mon = BCD2HEX(BCDMON);
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tm->tm_mday = BCD2HEX(BCDDAY);
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tm->tm_wday = BCD2HEX(BCDDATE);
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tm->tm_hour = BCD2HEX(BCDHOUR);
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tm->tm_min = BCD2HEX(BCDMIN);
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tm->tm_sec = BCD2HEX(BCDSEC);
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}
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RTCCON &= ~1;
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if(tm->tm_year >= 70)
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tm->tm_year += 1900;
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else
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tm->tm_year += 2000;
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return 0;
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}
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int rtc_set (struct rtc_time* tm)
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{
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if(tm->tm_year < 2000)
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tm->tm_year -= 1900;
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else
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tm->tm_year -= 2000;
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RTCCON |= 1;
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BCDYEAR = HEX2BCD(tm->tm_year);
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BCDMON = HEX2BCD(tm->tm_mon);
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BCDDAY = HEX2BCD(tm->tm_mday);
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BCDDATE = HEX2BCD(tm->tm_wday);
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BCDHOUR = HEX2BCD(tm->tm_hour);
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BCDMIN = HEX2BCD(tm->tm_min);
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BCDSEC = HEX2BCD(tm->tm_sec);
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RTCCON &= 1;
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return 0;
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}
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void rtc_reset (void)
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{
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RTCCON |= 1;
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BCDYEAR = 0;
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BCDMON = 0;
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BCDDAY = 0;
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BCDDATE = 0;
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BCDHOUR = 0;
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BCDMIN = 0;
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BCDSEC = 0;
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RTCCON &= 1;
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}
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/*
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I2C stuff
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*/
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/*
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* Initialization, must be called once on start up, may be called
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* repeatedly to change the speed and slave addresses.
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*/
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void i2c_init(int speed, int slaveaddr)
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{
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/*
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setting up I2C support
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*/
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unsigned int save_F,save_PF,rIICCON,rPCONA,rPDATA,rPCONF,rPUPF;
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save_F = PCONF;
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save_PF = PUPF;
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rPCONF = ((save_F & ~(0xF))| 0xa);
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rPUPF = (save_PF | 0x3);
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PCONF = rPCONF; /*PF0:IICSCL, PF1:IICSDA*/
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PUPF = rPUPF; /* Disable pull-up */
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/* Configuring pin for WC pin of EEprom */
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rPCONA = PCONA;
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rPCONA &= ~(1<<9);
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PCONA = rPCONA;
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rPDATA = PDATA;
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rPDATA &= ~(1<<9);
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PDATA = rPDATA;
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/*
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Enable ACK, IICCLK=MCLK/16, enable interrupt
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75MHz/16/(12+1) = 390625 Hz
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*/
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rIICCON=(1<<7)|(0<<6)|(1<<5)|(0xC);
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IICCON = rIICCON;
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IICADD = slaveaddr;
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}
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/*
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* Probe the given I2C chip address. Returns 0 if a chip responded,
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* not 0 on failure.
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*/
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int i2c_probe(uchar chip)
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{
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/*
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not implemented
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*/
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printf("i2c_probe chip %d\n", (int) chip);
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return -1;
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}
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/*
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* Read/Write interface:
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* chip: I2C chip address, range 0..127
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* addr: Memory (register) address within the chip
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* alen: Number of bytes to use for addr (typically 1, 2 for larger
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* memories, 0 for register type devices with only one
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* register)
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* buffer: Where to read/write the data
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* len: How many bytes to read/write
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*
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* Returns: 0 on success, not 0 on failure
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*/
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#define S3C44B0X_rIIC_INTPEND (1<<4)
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#define S3C44B0X_rIIC_LAST_RECEIV_BIT (1<<0)
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#define S3C44B0X_rIIC_INTERRUPT_ENABLE (1<<5)
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#define S3C44B0_IIC_TIMEOUT 100
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int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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int k, j, temp;
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u32 rIICSTAT;
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/*
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send the device offset
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*/
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rIICSTAT = 0xD0;
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IICSTAT = rIICSTAT;
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IICDS = chip; /* this is a write operation... */
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rIICSTAT |= (1<<5);
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IICSTAT = rIICSTAT;
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for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
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temp = IICCON;
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if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
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break;
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udelay(2000);
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}
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if (k==S3C44B0_IIC_TIMEOUT)
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return -1;
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/* wait and check ACK */
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temp = IICSTAT;
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if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
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return -1;
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IICDS = addr;
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IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
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/* wait and check ACK */
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for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
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temp = IICCON;
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if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
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break;
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udelay(2000);
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}
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if (k==S3C44B0_IIC_TIMEOUT)
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return -1;
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temp = IICSTAT;
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if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
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return -1;
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/*
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now we can start with the read operation...
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*/
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IICDS = chip | 0x01; /* this is a read operation... */
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rIICSTAT = 0x90; /*master recv*/
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rIICSTAT |= (1<<5);
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IICSTAT = rIICSTAT;
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IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
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/* wait and check ACK */
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for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
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temp = IICCON;
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if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
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break;
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udelay(2000);
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}
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if (k==S3C44B0_IIC_TIMEOUT)
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return -1;
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temp = IICSTAT;
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if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
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return -1;
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for (j=0; j<len-1; j++) {
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/*clear pending bit to resume */
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temp = IICCON & ~(S3C44B0X_rIIC_INTPEND);
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IICCON = temp;
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/* wait and check ACK */
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for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
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temp = IICCON;
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if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
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break;
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udelay(2000);
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}
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if (k==S3C44B0_IIC_TIMEOUT)
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return -1;
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buffer[j] = IICDS; /*save readed data*/
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} /*end for(j)*/
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/*
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reading the last data
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unset ACK generation
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*/
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temp = IICCON & ~(S3C44B0X_rIIC_INTPEND | (1<<7));
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IICCON = temp;
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/* wait but NOT check ACK */
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for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
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temp = IICCON;
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if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
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break;
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udelay(2000);
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}
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if (k==S3C44B0_IIC_TIMEOUT)
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return -1;
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buffer[j] = IICDS; /*save readed data*/
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rIICSTAT = 0x90; /*master recv*/
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/* Write operation Terminate sending STOP */
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IICSTAT = rIICSTAT;
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/*Clear Int Pending Bit to RESUME*/
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temp = IICCON;
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IICCON = temp & (~S3C44B0X_rIIC_INTPEND);
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IICCON = IICCON | (1<<7); /*restore ACK generation*/
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return 0;
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}
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int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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int j, k;
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u32 rIICSTAT, temp;
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/*
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send the device offset
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*/
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rIICSTAT = 0xD0;
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IICSTAT = rIICSTAT;
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IICDS = chip; /* this is a write operation... */
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rIICSTAT |= (1<<5);
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IICSTAT = rIICSTAT;
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IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
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/* wait and check ACK */
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for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
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temp = IICCON;
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if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
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break;
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udelay(2000);
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}
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if (k==S3C44B0_IIC_TIMEOUT)
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return -1;
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temp = IICSTAT;
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if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
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return -1;
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IICDS = addr;
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IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
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/* wait and check ACK */
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for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
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temp = IICCON;
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if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
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break;
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udelay(2000);
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}
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if (k==S3C44B0_IIC_TIMEOUT)
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return -1;
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temp = IICSTAT;
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if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
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return -1;
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/*
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now we can start with the read write operation
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*/
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for (j=0; j<len; j++) {
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IICDS = buffer[j]; /*prerare data to write*/
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/*clear pending bit to resume*/
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temp = IICCON & ~(S3C44B0X_rIIC_INTPEND);
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IICCON = temp;
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/* wait but NOT check ACK */
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for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
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temp = IICCON;
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if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
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break;
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udelay(2000);
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}
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if (k==S3C44B0_IIC_TIMEOUT)
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return -1;
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} /* end for(j) */
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/* sending stop to terminate */
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rIICSTAT = 0xD0; /*master send*/
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IICSTAT = rIICSTAT;
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/*Clear Int Pending Bit to RESUME*/
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temp = IICCON;
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IICCON = temp & (~S3C44B0X_rIIC_INTPEND);
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return 0;
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}
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