upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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25 lines
784 B
25 lines
784 B
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __AVR32_CACHE_H__
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#define __AVR32_CACHE_H__
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/*
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* Since the AVR32 architecture has a queryable cacheline size with a maximum
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* value of 256 we set the DMA buffer alignemnt requirement to this maximum
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* value. The board config can override this if it knows that the cacheline
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* size is a smaller value. AVR32 boards use the CONFIG_SYS_DCACHE_LINESZ
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* macro to specify cache line size, so if it is set we use it instead.
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*/
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#ifdef CONFIG_SYS_CACHELINE_SIZE
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#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
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#elif defined(CONFIG_SYS_DCACHE_LINESZ)
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#define ARCH_DMA_MINALIGN CONFIG_SYS_DCACHE_LINESZ
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#else
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#define ARCH_DMA_MINALIGN 256
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#endif
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#endif /* __AVR32_CACHE_H__ */
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