upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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298 lines
7.5 KiB
298 lines
7.5 KiB
/*
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* Board specific setup info
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*
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* (C) Copyright 2003
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* Texas Instruments, <www.ti.com>
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* Kshitij Gupta <Kshitij@ti.com>
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*
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* Modified for the NS9750 DevBoard by
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* (C) Copyright 2004 by FS Forth-Systeme GmbH.
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* Markus Pietrek <mpietrek@fsforth.de>
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* @References: [1] NS9750 Hardware Reference/December 2003
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* [2] ns9750_a.cmd from MAJIC configuration
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#if defined(CONFIG_NS9750DEV)
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# ifndef CONFIG_SKIP_LOWLEVEL_INIT
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# include <./ns9750_sys.h>
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# include <./ns9750_mem.h>
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# endif
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#endif
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/***********************************************************************
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* @Function: write_register_block
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* @Return: nothing
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* @Descr: Copies the register block of register_offset:register value to
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* the registers at base r0. The block is assumed to start in RAM at r1
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* and end at r2. The linked RAM base address of U-Boot is assumed to be
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* in r5 while the ROM base address we are running from is r6
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* Uses r3 and r4 as tempory registers
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***********************************************************************/
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.macro write_register_block
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@@ map the addresses to high memory
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sub r1, r1, r5
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add r1, r1, r6
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sub r2, r2, r5
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add r2, r2, r6
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@@ copy all
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1:
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@@ Write register/value pair starting at [r1] to register base r0
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ldr r3, [r1], #4
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ldr r4, [r1], #4
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str r4, [r0,r3]
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cmp r1, r2
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blt 1b
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.endm
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_TEXT_BASE:
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.word TEXT_BASE @ sdram load addr from config.mk
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_PHYS_FLASH:
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.word PHYS_FLASH_1 @ real flash address (without mirroring)
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_CAS_LATENCY:
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.word 0x00022000 @ for CAS2 latency
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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.globl platformsetup
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platformsetup:
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/* U-Boot may be linked to RAM at 0x780000. But this code will run in
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flash from 0x0. But in order to enable RAM we have to disable the
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mirror bit, therefore we have to jump to our real flash address
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beginning at PHYS_FLASH_1 (CS4 Base). Therefore,
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_run_at_real_flash_address may be 0x500003b0 while be linked to
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0x7803b0. So we must modify our linked addresses */
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@@ branch to high memory address, away from 0x0
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ldr r5, _TEXT_BASE
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ldr r6, _PHYS_FLASH
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ldr r0, =_run_at_real_flash_address
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sub r0, r0, r5
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add r0, r0, r6
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mov pc, r0
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nop @ for pipelining
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_run_at_real_flash_address:
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@@ now we are running > PHYS_FLASH_1, safe to enable memory controller
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@@ Write Memory Configuration Registers
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ldr r0, _NS9750_MEM_MODULE_BASE
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ldr r1, =_MEM_CONFIG_START
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ldr r2, =_MEM_CONFIG_END
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write_register_block
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@@ Give SDRAM some time to settle
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@@ @TODO. According to [2] it should be 2 AHB cycles. Check
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ldr r1, =0x50
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_sdram_settle:
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subs r1, r1, #1
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bne _sdram_settle
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_enable_mappings:
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@@ Enable SDRAM Mode
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ldr r1, =_MEM_MODE_START
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ldr r2, =_MEM_MODE_END
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write_register_block
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ldr r3, _CAS_LATENCY @ perform one read from SDRAM
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ldr r3, [r3]
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@@ Enable SDRAM and memory mappings
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ldr r1, =_MEM_ENABLE_START
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ldr r2, =_MEM_ENABLE_END
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write_register_block
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@@ Activate AHB monitor
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ldr r0, =NS9750_SYS_MODULE_BASE
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ldr r1, =_AHB_MONITOR_START
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ldr r2, =_AHB_MONITOR_END
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write_register_block
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_relocate_lr:
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/* lr and ip (from cpu_init_crit) are still based on 0x0, relocate it to
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PHYS_FLASH. */
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mov r1, ip
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add r1, r1, r6
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mov ip, r1
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mov r1, lr
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add r1, r1, r6
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mov lr, r1
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@@ back to arch calling code
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mov pc, lr
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.ltorg
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_NS9750_MEM_MODULE_BASE:
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.word NS9750_MEM_MODULE_BASE
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_MEM_CONFIG_START:
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/* Table of 2 32bit entries. First word is register address offset
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relative to NS9750_MEM_MODULE_BASE, second one is value. They are
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written in order of appearance */
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@@ Register values taken from [2]
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.word NS9750_MEM_CTRL
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.word NS9750_MEM_CTRL_E
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.word NS9750_MEM_DYN_REFRESH
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.word (0x6 & NS9750_MEM_DYN_REFRESH_MA)
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.word NS9750_MEM_DYN_READ_CFG
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.word (0x1 & NS9750_MEM_DYN_READ_CFG_MA)
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.word NS9750_MEM_DYN_TRP
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.word (0x1 & NS9750_MEM_DYN_TRP_MA)
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.word NS9750_MEM_DYN_TRAS
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.word (0x4 & NS9750_MEM_DYN_TRAS_MA)
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.word NS9750_MEM_DYN_TAPR
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.word (0x1 & NS9750_MEM_DYN_TRAS_MA)
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.word NS9750_MEM_DYN_TDAL
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.word (0x5 & NS9750_MEM_DYN_TDAL_MA)
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.word NS9750_MEM_DYN_TWR
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.word (0x1 & NS9750_MEM_DYN_TWR_MA)
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.word NS9750_MEM_DYN_TRC
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.word (0x6 & NS9750_MEM_DYN_TRC_MA)
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.word NS9750_MEM_DYN_TRFC
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.word (0x6 & NS9750_MEM_DYN_TRFC_MA)
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.word NS9750_MEM_DYN_TRRD
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.word (0x1 & NS9750_MEM_DYN_TRRD_MA)
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.word NS9750_MEM_DYN_TMRD
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.word (0x1 & NS9750_MEM_DYN_TMRD_MA)
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@@ CS 4
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.word NS9750_MEM_DYN_CFG(0)
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.word (NS9750_MEM_DYN_CFG_AM | \
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(0x280 & NS9750_MEM_DYN_CFG_AM_MA))
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.word NS9750_MEM_DYN_RAS_CAS(0)
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.word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
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(0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
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@@ CS 5
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.word NS9750_MEM_DYN_CFG(1)
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.word (NS9750_MEM_DYN_CFG_AM | \
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(0x280 & NS9750_MEM_DYN_CFG_AM_MA))
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.word NS9750_MEM_DYN_RAS_CAS(1)
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.word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
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(0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
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@@ CS 6
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.word NS9750_MEM_DYN_CFG(2)
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.word (NS9750_MEM_DYN_CFG_AM | \
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(0x280 & NS9750_MEM_DYN_CFG_AM_MA))
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.word NS9750_MEM_DYN_RAS_CAS(2)
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.word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
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(0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
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@@ CS 7
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.word NS9750_MEM_DYN_CFG(3)
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.word (NS9750_MEM_DYN_CFG_AM | \
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(0x280 & NS9750_MEM_DYN_CFG_AM_MA))
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.word NS9750_MEM_DYN_RAS_CAS(3)
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.word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
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(0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
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.word NS9750_MEM_DYN_CTRL
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.word (NS9750_MEM_DYN_CTRL_I_PALL | \
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NS9750_MEM_DYN_CTRL_SR | \
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NS9750_MEM_DYN_CTRL_CE )
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.word NS9750_MEM_DYN_REFRESH
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.word (0x1 & NS9750_MEM_DYN_REFRESH_MA)
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@@ No further register settings after refresh
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_MEM_CONFIG_END:
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_MEM_MODE_START:
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.word NS9750_MEM_DYN_REFRESH
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.word (0x30 & NS9750_MEM_DYN_REFRESH_MA)
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.word NS9750_MEM_DYN_CTRL
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.word (NS9750_MEM_DYN_CTRL_I_MODE | \
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NS9750_MEM_DYN_CTRL_SR | \
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NS9750_MEM_DYN_CTRL_CE )
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_MEM_MODE_END:
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_MEM_ENABLE_START:
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.word NS9750_MEM_DYN_CTRL
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.word (NS9750_MEM_DYN_CTRL_I_NORMAL | \
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NS9750_MEM_DYN_CTRL_SR | \
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NS9750_MEM_DYN_CTRL_CE )
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@@ CS 4
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.word NS9750_MEM_DYN_CFG(0)
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.word (NS9750_MEM_DYN_CFG_BDMC | \
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NS9750_MEM_DYN_CFG_AM | \
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(0x280 & NS9750_MEM_DYN_CFG_AM_MA))
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@@ CS 5
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.word NS9750_MEM_DYN_CFG(1)
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.word (NS9750_MEM_DYN_CFG_BDMC | \
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NS9750_MEM_DYN_CFG_AM | \
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(0x280 & NS9750_MEM_DYN_CFG_AM_MA))
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@@ CS 6
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.word NS9750_MEM_DYN_CFG(2)
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.word (NS9750_MEM_DYN_CFG_BDMC | \
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NS9750_MEM_DYN_CFG_AM | \
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(0x280 & NS9750_MEM_DYN_CFG_AM_MA))
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@@ CS 7
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.word NS9750_MEM_DYN_CFG(3)
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.word (NS9750_MEM_DYN_CFG_BDMC | \
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NS9750_MEM_DYN_CFG_AM | \
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(0x280 & NS9750_MEM_DYN_CFG_AM_MA))
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_MEM_ENABLE_END:
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_AHB_MONITOR_START:
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.word NS9750_SYS_AHB_TIMEOUT
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.word 0x01000100 @ @TODO not calculated yet
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.word NS9750_SYS_AHB_MON
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.word (NS9750_SYS_AHB_MON_BMTC_GEN_IRQ | \
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NS9750_SYS_AHB_MON_BATC_GEN_IRQ)
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_AHB_MONITOR_END:
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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