upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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85 lines
1.6 KiB
85 lines
1.6 KiB
/*
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* Copyright (c) 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __S5M8767_H_
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#define __S5M8767_H_
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enum s5m8767_regnum {
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S5M8767_BUCK1 = 0,
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S5M8767_BUCK2,
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S5M8767_BUCK3,
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S5M8767_BUCK4,
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S5M8767_BUCK5,
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S5M8767_BUCK6,
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S5M8767_BUCK7,
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S5M8767_BUCK8,
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S5M8767_BUCK9,
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S5M8767_LDO1,
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S5M8767_LDO2,
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S5M8767_LDO3,
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S5M8767_LDO4,
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S5M8767_LDO5,
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S5M8767_LDO6,
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S5M8767_LDO7,
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S5M8767_LDO8,
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S5M8767_LDO9,
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S5M8767_LDO10,
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S5M8767_LDO11,
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S5M8767_LDO12,
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S5M8767_LDO13,
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S5M8767_LDO14,
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S5M8767_LDO15,
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S5M8767_LDO16,
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S5M8767_LDO17,
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S5M8767_LDO18,
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S5M8767_LDO19,
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S5M8767_LDO20,
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S5M8767_LDO21,
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S5M8767_LDO22,
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S5M8767_LDO23,
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S5M8767_LDO24,
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S5M8767_LDO25,
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S5M8767_LDO26,
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S5M8767_LDO27,
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S5M8767_LDO28,
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S5M8767_EN32KHZ_CP,
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S5M8767_NUM_OF_REGS,
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};
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struct sec_voltage_desc {
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int max;
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int min;
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int step;
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};
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/**
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* struct s5m8767_para - s5m8767 register parameters
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* @param vol_addr i2c address of the given buck/ldo register
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* @param vol_bitpos bit position to be set or clear within register
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* @param vol_bitmask bit mask value
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* @param reg_enaddr control register address, which enable the given
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* given buck/ldo.
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* @param reg_enbiton value to be written to buck/ldo to make it ON
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* @param vol Voltage information
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*/
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struct s5m8767_para {
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enum s5m8767_regnum regnum;
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u8 vol_addr;
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u8 vol_bitpos;
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u8 vol_bitmask;
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u8 reg_enaddr;
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u8 reg_enbiton;
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const struct sec_voltage_desc *vol;
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};
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/* Drivers name */
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#define S5M8767_LDO_DRIVER "s5m8767_ldo"
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#define S5M8767_BUCK_DRIVER "s5m8767_buck"
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int s5m8767_enable_32khz_cp(struct udevice *dev);
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#endif /* __S5M8767_PMIC_H_ */
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