upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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510 lines
12 KiB
510 lines
12 KiB
/*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/i8259.h>
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#include <asm/ibmpc.h>
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#include <asm/interrupt.h>
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struct idt_entry {
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u16 base_low;
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u16 selector;
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u8 res;
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u8 access;
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u16 base_high;
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} __attribute__ ((packed));
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struct idt_entry idt[256];
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#define MAX_IRQ 16
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typedef struct irq_handler {
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struct irq_handler *next;
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interrupt_handler_t* isr_func;
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void *isr_data;
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} irq_handler_t;
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#define IRQ_DISABLED 1
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typedef struct {
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irq_handler_t *handler;
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unsigned long status;
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} irq_desc_t;
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static irq_desc_t irq_table[MAX_IRQ];
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asm ("irq_return:\n"
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" addl $4, %esp\n"
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" popa\n"
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" iret\n");
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asm ("exp_return:\n"
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" addl $12, %esp\n"
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" pop %esp\n"
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" popa\n"
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" iret\n");
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char exception_stack[4096];
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#define DECLARE_INTERRUPT(x) \
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asm(".globl irq_"#x"\n" \
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"irq_"#x":\n" \
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"pusha \n" \
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"pushl $"#x"\n" \
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"pushl $irq_return\n" \
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"jmp do_irq\n"); \
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void __attribute__ ((regparm(0))) irq_##x(void)
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#define DECLARE_EXCEPTION(x, f) \
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asm(".globl exp_"#x"\n" \
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"exp_"#x":\n" \
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"pusha \n" \
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"movl %esp, %ebx\n" \
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"movl $exception_stack, %eax\n" \
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"movl %eax, %esp \n" \
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"pushl %ebx\n" \
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"movl 32(%esp), %ebx\n" \
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"xorl %edx, %edx\n" \
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"movw 36(%esp), %dx\n" \
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"pushl %edx\n" \
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"pushl %ebx\n" \
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"pushl $"#x"\n" \
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"pushl $exp_return\n" \
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"jmp "#f"\n"); \
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void __attribute__ ((regparm(0))) exp_##x(void)
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DECLARE_EXCEPTION(0, divide_exception_entry); /* Divide exception */
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DECLARE_EXCEPTION(1, debug_exception_entry); /* Debug exception */
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DECLARE_EXCEPTION(2, nmi_entry); /* NMI */
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DECLARE_EXCEPTION(3, unknown_exception_entry); /* Breakpoint/Coprocessor Error */
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DECLARE_EXCEPTION(4, unknown_exception_entry); /* Overflow */
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DECLARE_EXCEPTION(5, unknown_exception_entry); /* Bounds */
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DECLARE_EXCEPTION(6, invalid_instruction_entry); /* Invalid instruction */
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DECLARE_EXCEPTION(7, unknown_exception_entry); /* Device not present */
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DECLARE_EXCEPTION(8, double_fault_entry); /* Double fault */
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DECLARE_EXCEPTION(9, unknown_exception_entry); /* Co-processor segment overrun */
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DECLARE_EXCEPTION(10, invalid_tss_exception_entry);/* Invalid TSS */
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DECLARE_EXCEPTION(11, seg_fault_entry); /* Segment not present */
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DECLARE_EXCEPTION(12, stack_fault_entry); /* Stack overflow */
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DECLARE_EXCEPTION(13, gpf_entry); /* GPF */
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DECLARE_EXCEPTION(14, page_fault_entry); /* PF */
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DECLARE_EXCEPTION(15, unknown_exception_entry); /* Reserved */
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DECLARE_EXCEPTION(16, fp_exception_entry); /* Floating point */
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DECLARE_EXCEPTION(17, alignment_check_entry); /* alignment check */
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DECLARE_EXCEPTION(18, machine_check_entry); /* machine check */
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DECLARE_EXCEPTION(19, unknown_exception_entry); /* Reserved */
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DECLARE_EXCEPTION(20, unknown_exception_entry); /* Reserved */
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DECLARE_EXCEPTION(21, unknown_exception_entry); /* Reserved */
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DECLARE_EXCEPTION(22, unknown_exception_entry); /* Reserved */
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DECLARE_EXCEPTION(23, unknown_exception_entry); /* Reserved */
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DECLARE_EXCEPTION(24, unknown_exception_entry); /* Reserved */
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DECLARE_EXCEPTION(25, unknown_exception_entry); /* Reserved */
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DECLARE_EXCEPTION(26, unknown_exception_entry); /* Reserved */
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DECLARE_EXCEPTION(27, unknown_exception_entry); /* Reserved */
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DECLARE_EXCEPTION(28, unknown_exception_entry); /* Reserved */
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DECLARE_EXCEPTION(29, unknown_exception_entry); /* Reserved */
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DECLARE_EXCEPTION(30, unknown_exception_entry); /* Reserved */
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DECLARE_EXCEPTION(31, unknown_exception_entry); /* Reserved */
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DECLARE_INTERRUPT(0);
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DECLARE_INTERRUPT(1);
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DECLARE_INTERRUPT(3);
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DECLARE_INTERRUPT(4);
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DECLARE_INTERRUPT(5);
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DECLARE_INTERRUPT(6);
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DECLARE_INTERRUPT(7);
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DECLARE_INTERRUPT(8);
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DECLARE_INTERRUPT(9);
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DECLARE_INTERRUPT(10);
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DECLARE_INTERRUPT(11);
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DECLARE_INTERRUPT(12);
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DECLARE_INTERRUPT(13);
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DECLARE_INTERRUPT(14);
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DECLARE_INTERRUPT(15);
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void __attribute__ ((regparm(0))) default_isr(void);
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asm ("default_isr: iret\n");
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void disable_irq(int irq)
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{
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if (irq >= MAX_IRQ) {
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return;
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}
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irq_table[irq].status |= IRQ_DISABLED;
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}
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void enable_irq(int irq)
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{
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if (irq >= MAX_IRQ) {
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return;
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}
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irq_table[irq].status &= ~IRQ_DISABLED;
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}
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/* masks one specific IRQ in the PIC */
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static void unmask_irq(int irq)
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{
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int imr_port;
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if (irq >= MAX_IRQ) {
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return;
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}
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if (irq > 7) {
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imr_port = SLAVE_PIC + IMR;
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} else {
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imr_port = MASTER_PIC + IMR;
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}
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outb(inb(imr_port)&~(1<<(irq&7)), imr_port);
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}
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/* unmasks one specific IRQ in the PIC */
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static void mask_irq(int irq)
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{
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int imr_port;
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if (irq >= MAX_IRQ) {
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return;
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}
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if (irq > 7) {
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imr_port = SLAVE_PIC + IMR;
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} else {
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imr_port = MASTER_PIC + IMR;
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}
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outb(inb(imr_port)|(1<<(irq&7)), imr_port);
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}
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/* issue a Specific End Of Interrupt instruciton */
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static void specific_eoi(int irq)
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{
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/* If it is on the slave PIC this have to be performed on
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* both the master and the slave PICs */
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if (irq > 7) {
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outb(OCW2_SEOI|(irq&7), SLAVE_PIC + OCW2);
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irq = SEOI_IR2; /* also do IR2 on master */
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}
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outb(OCW2_SEOI|irq, MASTER_PIC + OCW2);
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}
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void __attribute__ ((regparm(0))) do_irq(int irq)
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{
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mask_irq(irq);
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if (irq_table[irq].status & IRQ_DISABLED) {
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unmask_irq(irq);
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specific_eoi(irq);
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return;
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}
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if (NULL != irq_table[irq].handler) {
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irq_handler_t *handler;
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for (handler = irq_table[irq].handler;
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NULL!= handler; handler = handler->next) {
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handler->isr_func(handler->isr_data);
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}
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} else {
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if ((irq & 7) != 7) {
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printf("Spurious irq %d\n", irq);
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}
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}
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unmask_irq(irq);
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specific_eoi(irq);
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}
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void __attribute__ ((regparm(0))) unknown_exception_entry(int cause, int ip, int seg)
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{
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printf("Unknown Exception %d at %04x:%08x\n", cause, seg, ip);
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}
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void __attribute__ ((regparm(0))) divide_exception_entry(int cause, int ip, int seg)
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{
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printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip);
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while(1);
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}
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void __attribute__ ((regparm(0))) debug_exception_entry(int cause, int ip, int seg)
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{
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printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip);
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}
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void __attribute__ ((regparm(0))) nmi_entry(int cause, int ip, int seg)
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{
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printf("NMI Interrupt at %04x:%08x\n", seg, ip);
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}
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void __attribute__ ((regparm(0))) invalid_instruction_entry(int cause, int ip, int seg)
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{
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printf("Invalid Instruction at %04x:%08x\n", seg, ip);
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while(1);
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}
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void __attribute__ ((regparm(0))) double_fault_entry(int cause, int ip, int seg)
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{
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printf("Double fault at %04x:%08x\n", seg, ip);
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while(1);
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}
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void __attribute__ ((regparm(0))) invalid_tss_exception_entry(int cause, int ip, int seg)
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{
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printf("Invalid TSS at %04x:%08x\n", seg, ip);
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}
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void __attribute__ ((regparm(0))) seg_fault_entry(int cause, int ip, int seg)
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{
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printf("Segmentation fault at %04x:%08x\n", seg, ip);
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while(1);
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}
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void __attribute__ ((regparm(0))) stack_fault_entry(int cause, int ip, int seg)
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{
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printf("Stack fault at %04x:%08x\n", seg, ip);
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while(1);
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}
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void __attribute__ ((regparm(0))) gpf_entry(int cause, int ip, int seg)
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{
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printf("General protection fault at %04x:%08x\n", seg, ip);
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}
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void __attribute__ ((regparm(0))) page_fault_entry(int cause, int ip, int seg)
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{
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printf("Page fault at %04x:%08x\n", seg, ip);
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while(1);
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}
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void __attribute__ ((regparm(0))) fp_exception_entry(int cause, int ip, int seg)
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{
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printf("Floating point exception at %04x:%08x\n", seg, ip);
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}
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void __attribute__ ((regparm(0))) alignment_check_entry(int cause, int ip, int seg)
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{
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printf("Alignment check at %04x:%08x\n", seg, ip);
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}
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void __attribute__ ((regparm(0))) machine_check_entry(int cause, int ip, int seg)
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{
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printf("Machine check exception at %04x:%08x\n", seg, ip);
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}
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void irq_install_handler(int ino, interrupt_handler_t *func, void *pdata)
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{
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int status;
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if (ino>MAX_IRQ) {
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return;
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}
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if (NULL != irq_table[ino].handler) {
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return;
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}
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status = disable_interrupts();
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irq_table[ino].handler = malloc(sizeof(irq_handler_t));
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if (NULL == irq_table[ino].handler) {
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return;
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}
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memset(irq_table[ino].handler, 0, sizeof(irq_handler_t));
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irq_table[ino].handler->isr_func = func;
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irq_table[ino].handler->isr_data = pdata;
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if (status) {
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enable_interrupts();
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}
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unmask_irq(ino);
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return;
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}
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void irq_free_handler(int ino)
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{
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int status;
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if (ino>MAX_IRQ) {
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return;
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}
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status = disable_interrupts();
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mask_irq(ino);
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if (NULL == irq_table[ino].handler) {
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return;
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}
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free(irq_table[ino].handler);
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irq_table[ino].handler=NULL;
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if (status) {
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enable_interrupts();
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}
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return;
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}
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asm ("idt_ptr:\n"
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".word 0x800\n" /* size of the table 8*256 bytes */
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".long idt\n" /* offset */
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".word 0x18\n");/* data segment */
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void set_vector(int intnum, void *routine)
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{
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idt[intnum].base_high = (u16)((u32)(routine)>>16);
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idt[intnum].base_low = (u16)((u32)(routine)&0xffff);
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}
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int interrupt_init(void)
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{
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int i;
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/* Just in case... */
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disable_interrupts();
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/* Initialize the IDT and stuff */
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memset(irq_table, 0, sizeof(irq_table));
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/* Setup the IDT */
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for (i=0;i<256;i++) {
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idt[i].access = 0x8e;
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idt[i].res = 0;
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idt[i].selector = 0x10;
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set_vector(i, default_isr);
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}
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asm ("cs lidt idt_ptr\n");
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/* Setup exceptions */
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set_vector(0x00, exp_0);
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set_vector(0x01, exp_1);
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set_vector(0x02, exp_2);
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set_vector(0x03, exp_3);
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set_vector(0x04, exp_4);
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set_vector(0x05, exp_5);
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set_vector(0x06, exp_6);
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set_vector(0x07, exp_7);
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set_vector(0x08, exp_8);
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set_vector(0x09, exp_9);
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set_vector(0x0a, exp_10);
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set_vector(0x0b, exp_11);
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set_vector(0x0c, exp_12);
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set_vector(0x0d, exp_13);
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set_vector(0x0e, exp_14);
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set_vector(0x0f, exp_15);
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set_vector(0x10, exp_16);
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set_vector(0x11, exp_17);
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set_vector(0x12, exp_18);
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set_vector(0x13, exp_19);
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set_vector(0x14, exp_20);
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set_vector(0x15, exp_21);
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set_vector(0x16, exp_22);
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set_vector(0x17, exp_23);
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set_vector(0x18, exp_24);
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set_vector(0x19, exp_25);
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set_vector(0x1a, exp_26);
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set_vector(0x1b, exp_27);
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set_vector(0x1c, exp_28);
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set_vector(0x1d, exp_29);
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set_vector(0x1e, exp_30);
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set_vector(0x1f, exp_31);
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/* Setup interrupts */
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set_vector(0x20, irq_0);
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set_vector(0x21, irq_1);
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set_vector(0x23, irq_3);
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set_vector(0x24, irq_4);
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set_vector(0x25, irq_5);
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set_vector(0x26, irq_6);
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set_vector(0x27, irq_7);
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set_vector(0x28, irq_8);
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set_vector(0x29, irq_9);
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set_vector(0x2a, irq_10);
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set_vector(0x2b, irq_11);
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set_vector(0x2c, irq_12);
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set_vector(0x2d, irq_13);
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set_vector(0x2e, irq_14);
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set_vector(0x2f, irq_15);
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/* vectors 0x30-0x3f are reserved for irq 16-31 */
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/* Mask all interrupts */
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outb(0xff, MASTER_PIC + IMR);
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outb(0xff, SLAVE_PIC + IMR);
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/* Master PIC */
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outb(ICW1_SEL|ICW1_EICW4, MASTER_PIC + ICW1);
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outb(0x20, MASTER_PIC + ICW2); /* Place master PIC interrupts at INT20 */
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outb(IR2, MASTER_PIC + ICW3); /* ICW3, One slevc PIC is present */
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outb(ICW4_PM, MASTER_PIC + ICW4);
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for (i=0;i<8;i++) {
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outb(OCW2_SEOI|i, MASTER_PIC + OCW2);
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}
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/* Slave PIC */
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outb(ICW1_SEL|ICW1_EICW4, SLAVE_PIC + ICW1);
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outb(0x28, SLAVE_PIC + ICW2); /* Place slave PIC interrupts at INT28 */
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outb(0x02, SLAVE_PIC + ICW3); /* Slave ID */
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outb(ICW4_PM, SLAVE_PIC + ICW4);
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for (i=0;i<8;i++) {
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outb(OCW2_SEOI|i, SLAVE_PIC + OCW2);
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}
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/* enable cascade interrerupt */
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outb(0xfb, MASTER_PIC + IMR);
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outb(0xff, SLAVE_PIC + IMR);
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/* It is now safe to enable interrupts */
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enable_interrupts();
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return 0;
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}
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void enable_interrupts(void)
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{
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asm("sti\n");
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}
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int disable_interrupts(void)
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{
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long flags;
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asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
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return (flags&0x200); /* IE flags is bit 9 */
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}
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|