upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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239 lines
6.3 KiB
239 lines
6.3 KiB
/*
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* U-boot - traps.c Routines related to interrupts and exceptions
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*
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* Copyright (c) 2005-2007 Analog Devices Inc.
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*
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* This file is based on
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* No original Copyright holder listed,
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* Probabily original (C) Roman Zippel (assigned DJD, 1999)
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*
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* Copyright 2003 Metrowerks - for Blackfin
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* Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
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* Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
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*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <linux/types.h>
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#include <asm/errno.h>
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#include <asm/irq.h>
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#include <asm/system.h>
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#include <asm/traps.h>
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#include <asm/machdep.h>
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#include "cpu.h"
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#include <asm/arch/anomaly.h>
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#include <asm/cplb.h>
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#include <asm/io.h>
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void init_IRQ(void)
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{
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blackfin_init_IRQ();
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return;
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}
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void process_int(unsigned long vec, struct pt_regs *fp)
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{
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printf("interrupt\n");
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return;
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}
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extern unsigned int icplb_table[page_descriptor_table_size][2];
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extern unsigned int dcplb_table[page_descriptor_table_size][2];
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unsigned long last_cplb_fault_retx;
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static unsigned int cplb_sizes[4] =
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{ 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 };
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void trap_c(struct pt_regs *regs)
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{
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unsigned int addr;
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unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
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unsigned int i, j, size, *I0, *I1;
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unsigned short data = 0;
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switch (trapnr) {
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/* 0x26 - Data CPLB Miss */
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case VEC_CPLB_M:
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#ifdef ANOMALY_05000261
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/*
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* Work around an anomaly: if we see a new DCPLB fault, return
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* without doing anything. Then, if we get the same fault again,
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* handle it.
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*/
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addr = last_cplb_fault_retx;
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last_cplb_fault_retx = regs->retx;
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printf("this time, curr = 0x%08x last = 0x%08x\n", addr,
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last_cplb_fault_retx);
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if (addr != last_cplb_fault_retx)
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goto trap_c_return;
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#endif
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data = 1;
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case VEC_CPLB_I_M:
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if (data)
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addr = *pDCPLB_FAULT_ADDR;
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else
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addr = *pICPLB_FAULT_ADDR;
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for (i = 0; i < page_descriptor_table_size; i++) {
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if (data) {
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size = cplb_sizes[dcplb_table[i][1] >> 16];
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j = dcplb_table[i][0];
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} else {
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size = cplb_sizes[icplb_table[i][1] >> 16];
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j = icplb_table[i][0];
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}
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if ((j <= addr) && ((j + size) > addr)) {
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debug("found %i 0x%08x\n", i, j);
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break;
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}
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}
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if (i == page_descriptor_table_size) {
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printf("something is really wrong\n");
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do_reset(NULL, 0, 0, NULL);
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}
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/* Turn the cache off */
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if (data) {
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sync();
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asm(" .align 8; ");
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*(unsigned int *)DMEM_CONTROL &=
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~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
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sync();
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} else {
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sync();
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asm(" .align 8; ");
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*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
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sync();
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}
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if (data) {
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I0 = (unsigned int *)DCPLB_ADDR0;
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I1 = (unsigned int *)DCPLB_DATA0;
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} else {
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I0 = (unsigned int *)ICPLB_ADDR0;
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I1 = (unsigned int *)ICPLB_DATA0;
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}
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j = 0;
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while (*I1 & CPLB_LOCK) {
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debug("skipping %i %08p - %08x\n", j, I1, *I1);
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*I0++;
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*I1++;
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j++;
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}
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debug("remove %i 0x%08x 0x%08x\n", j, *I0, *I1);
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for (; j < 15; j++) {
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debug("replace %i 0x%08x 0x%08x\n", j, I0, I0 + 1);
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*I0++ = *(I0 + 1);
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*I1++ = *(I1 + 1);
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}
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if (data) {
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*I0 = dcplb_table[i][0];
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*I1 = dcplb_table[i][1];
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I0 = (unsigned int *)DCPLB_ADDR0;
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I1 = (unsigned int *)DCPLB_DATA0;
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} else {
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*I0 = icplb_table[i][0];
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*I1 = icplb_table[i][1];
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I0 = (unsigned int *)ICPLB_ADDR0;
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I1 = (unsigned int *)ICPLB_DATA0;
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}
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for (j = 0; j < 16; j++) {
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debug("%i 0x%08x 0x%08x\n", j, *I0++, *I1++);
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}
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/* Turn the cache back on */
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if (data) {
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j = *(unsigned int *)DMEM_CONTROL;
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sync();
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asm(" .align 8; ");
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*(unsigned int *)DMEM_CONTROL =
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ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
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sync();
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} else {
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sync();
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asm(" .align 8; ");
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*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
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sync();
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}
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break;
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default:
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/* All traps come here */
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printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
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printf("stack frame=0x%x, ", (unsigned int)regs);
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printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
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dump(regs);
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printf("\n\n");
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printf("Unhandled IRQ or exceptions!\n");
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printf("Please reset the board \n");
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do_reset(NULL, 0, 0, NULL);
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}
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trap_c_return:
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return;
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}
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void dump(struct pt_regs *fp)
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{
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debug("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n", fp->rete,
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fp->retn, fp->retx, fp->rets);
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debug("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
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debug("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp);
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debug("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n", fp->r0,
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fp->r1, fp->r2, fp->r3);
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debug("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n", fp->r4,
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fp->r5, fp->r6, fp->r7);
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debug("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n", fp->p0,
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fp->p1, fp->p2, fp->p3);
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debug("P4: %08lx P5: %08lx FP: %08lx\n", fp->p4, fp->p5, fp->fp);
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debug("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
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fp->a0w, fp->a0x, fp->a1w, fp->a1x);
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debug("LB0: %08lx LT0: %08lx LC0: %08lx\n", fp->lb0, fp->lt0,
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fp->lc0);
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debug("LB1: %08lx LT1: %08lx LC1: %08lx\n", fp->lb1, fp->lt1,
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fp->lc1);
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debug("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n", fp->b0, fp->l0,
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fp->m0, fp->i0);
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debug("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n", fp->b1, fp->l1,
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fp->m1, fp->i1);
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debug("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n", fp->b2, fp->l2,
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fp->m2, fp->i2);
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debug("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n", fp->b3, fp->l3,
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fp->m3, fp->i3);
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debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
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debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
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}
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