upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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140 lines
3.6 KiB
140 lines
3.6 KiB
/*
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*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/immap.h>
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#include <asm/rtc.h>
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f(void)
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{
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volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
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scm1->mpr = 0x77777777;
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scm1->pacra = 0;
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scm1->pacrb = 0;
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scm1->pacrc = 0;
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scm1->pacrd = 0;
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scm1->pacre = 0;
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scm1->pacrf = 0;
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scm1->pacrg = 0;
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/* FlexBus */
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gpio->par_be =
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GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 |
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GPIO_PAR_BE_BE0_BE0;
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gpio->par_fbctl =
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GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW |
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GPIO_PAR_FBCTL_TS_TS;
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#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
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fbcs->csar0 = CFG_CS0_BASE;
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fbcs->cscr0 = CFG_CS0_CTRL;
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fbcs->csmr0 = CFG_CS0_MASK;
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#endif
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#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
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/* Latch chipselect */
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fbcs->csar1 = CFG_CS1_BASE;
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fbcs->cscr1 = CFG_CS1_CTRL;
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fbcs->csmr1 = CFG_CS1_MASK;
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#endif
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#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
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fbcs->csar2 = CFG_CS2_BASE;
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fbcs->cscr2 = CFG_CS2_CTRL;
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fbcs->csmr2 = CFG_CS2_MASK;
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#endif
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#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
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fbcs->csar3 = CFG_CS3_BASE;
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fbcs->cscr3 = CFG_CS3_CTRL;
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fbcs->csmr3 = CFG_CS3_MASK;
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#endif
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#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
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fbcs->csar4 = CFG_CS4_BASE;
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fbcs->cscr4 = CFG_CS4_CTRL;
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fbcs->csmr4 = CFG_CS4_MASK;
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#endif
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#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
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fbcs->csar5 = CFG_CS5_BASE;
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fbcs->cscr5 = CFG_CS5_CTRL;
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fbcs->csmr5 = CFG_CS5_MASK;
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#endif
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#ifdef CONFIG_FSL_I2C
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gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
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#endif
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icache_enable();
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r(void)
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{
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#ifdef CONFIG_MCFTMR
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volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
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volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
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u32 oscillator = CFG_RTC_OSCILLATOR;
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rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF;
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rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF;
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#endif
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return (0);
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}
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void uart_port_conf(void)
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{
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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/* Setup Ports: */
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switch (CFG_UART_PORT) {
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case 0:
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gpio->par_uart =
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(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
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break;
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case 1:
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gpio->par_uart =
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(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
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break;
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}
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}
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