upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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77 lines
2.2 KiB
77 lines
2.2 KiB
/*
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* defBF533_extn.h
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*
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* This file is subject to the terms and conditions of the GNU Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Non-GPL License also available as part of VisualDSP++
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*
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* http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
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*
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* (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
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*
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* This file under source code control, please send bugs or changes to:
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* dsptools.support@analog.com
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*
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*/
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#ifndef _DEF_BF533_EXTN_H
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#define _DEF_BF533_EXTN_H
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/* define macro for offset */
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#define OFFSET_( x ) ((x) & 0x0000FFFF)
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/* Delay inserted for PLL transition */
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#define PLL_DELAY 0x1000
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#define L1_ISRAM 0xFFA00000
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#define L1_ISRAM_END 0xFFA10000
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#define DATA_BANKA_SRAM 0xFF800000
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#define DATA_BANKA_SRAM_END 0xFF808000
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#define DATA_BANKB_SRAM 0xFF900000
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#define DATA_BANKB_SRAM_END 0xFF908000
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#define SYSMMR_BASE 0xFFC00000
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#define WDSIZE16 0x00000004
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/* Event Vector Table Address */
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#define EVT_EMULATION_ADDR 0xffe02000
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#define EVT_RESET_ADDR 0xffe02004
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#define EVT_NMI_ADDR 0xffe02008
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#define EVT_EXCEPTION_ADDR 0xffe0200c
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#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010
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#define EVT_HARDWARE_ERROR_ADDR 0xffe02014
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#define EVT_TIMER_ADDR 0xffe02018
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#define EVT_IVG7_ADDR 0xffe0201c
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#define EVT_IVG8_ADDR 0xffe02020
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#define EVT_IVG9_ADDR 0xffe02024
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#define EVT_IVG10_ADDR 0xffe02028
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#define EVT_IVG11_ADDR 0xffe0202c
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#define EVT_IVG12_ADDR 0xffe02030
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#define EVT_IVG13_ADDR 0xffe02034
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#define EVT_IVG14_ADDR 0xffe02038
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#define EVT_IVG15_ADDR 0xffe0203c
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#define EVT_OVERRIDE_ADDR 0xffe02100
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/* IMASK Bit values */
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#define IVG15_POS 0x00008000
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#define IVG14_POS 0x00004000
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#define IVG13_POS 0x00002000
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#define IVG12_POS 0x00001000
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#define IVG11_POS 0x00000800
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#define IVG10_POS 0x00000400
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#define IVG9_POS 0x00000200
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#define IVG8_POS 0x00000100
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#define IVG7_POS 0x00000080
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#define IVGTMR_POS 0x00000040
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#define IVGHW_POS 0x00000020
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#define WDOG_TMR_DISABLE (0xAD << 4)
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#define ICTL_RST 0x00000000
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#define ICTL_NMI 0x00000002
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#define ICTL_GP 0x00000004
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#define ICTL_DISABLE 0x00000003
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/* Watch Dog timer values setup */
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#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE
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#endif /* _DEF_BF533_EXTN_H */
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