upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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215 lines
5.6 KiB
215 lines
5.6 KiB
/*
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* board/renesas/ulcb/ulcb.c
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* This file is ULCB board support.
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*
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* Copyright (C) 2017 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <netdev.h>
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#include <dm.h>
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#include <dm/platform_data/serial_sh.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rcar-mstp.h>
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#include <asm/arch/sh_sdhi.h>
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#include <i2c.h>
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#include <mmc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define CPGWPCR 0xE6150904
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#define CPGWPR 0xE615090C
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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void s_init(void)
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{
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
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/* Watchdog init */
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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writel(0xA5A50000, CPGWPCR);
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writel(0xFFFFFFFF, CPGWPR);
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}
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#define GSX_MSTP112 BIT(12) /* 3DG */
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#define TMU0_MSTP125 BIT(25) /* secure */
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#define TMU1_MSTP124 BIT(24) /* non-secure */
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#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
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#define DVFS_MSTP926 BIT(26)
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#define HSUSB_MSTP704 BIT(4) /* HSUSB */
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int board_early_init_f(void)
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{
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/* TMU0,1 */ /* which use ? */
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
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#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
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/* DVFS for reset */
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mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
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#endif
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return 0;
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}
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/* SYSC */
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/* R/- 32 Power status register 2(3DG) */
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#define SYSC_PWRSR2 0xE6180100
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/* -/W 32 Power resume control register 2 (3DG) */
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#define SYSC_PWRONCR2 0xE618010C
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/* HSUSB block registers */
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#define HSUSB_REG_LPSTS 0xE6590102
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#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
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#define HSUSB_REG_UGCTRL2 0xE6590184
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#define HSUSB_REG_UGCTRL2_USB0SEL 0x30
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#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
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#ifdef CONFIG_SH_GPIO_PFC
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/* Init PFC controller */
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#if defined(CONFIG_R8A7795)
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r8a7795_pinmux_init();
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#elif defined(CONFIG_R8A7796)
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r8a7796_pinmux_init();
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#endif
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#endif
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/* USB1 pull-up */
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setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
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/* Configure the HSUSB block */
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mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
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/* Choice USB0SEL */
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clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
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HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
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/* low power status */
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setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
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#ifdef CONFIG_RENESAS_RAVB
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/* EtherAVB Enable */
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/* GPSR2 */
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gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
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gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
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gpio_request(GPIO_GFN_AVB_LINK, NULL);
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gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
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gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
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gpio_request(GPIO_GFN_AVB_MDC, NULL);
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/* IPSR0 */
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gpio_request(GPIO_IFN_AVB_MDC, NULL);
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gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
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gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
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gpio_request(GPIO_IFN_AVB_LINK, NULL);
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gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
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gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
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/* IPSR1 */
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gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
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/* IPSR2 */
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gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
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/* IPSR3 */
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gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);
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/* AVB_PHY_RST */
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gpio_request(GPIO_GP_2_10, NULL);
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gpio_direction_output(GPIO_GP_2_10, 0);
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mdelay(20);
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gpio_set_value(GPIO_GP_2_10, 1);
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udelay(1);
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#endif
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#ifdef CONFIG_MMC
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/* SDHI0 */
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gpio_request(GPIO_GFN_SD0_DAT0, NULL);
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gpio_request(GPIO_GFN_SD0_DAT1, NULL);
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gpio_request(GPIO_GFN_SD0_DAT2, NULL);
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gpio_request(GPIO_GFN_SD0_DAT3, NULL);
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gpio_request(GPIO_GFN_SD0_CLK, NULL);
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gpio_request(GPIO_GFN_SD0_CMD, NULL);
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gpio_request(GPIO_GFN_SD0_CD, NULL);
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gpio_request(GPIO_GFN_SD0_WP, NULL);
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gpio_request(GPIO_GP_5_2, NULL);
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gpio_request(GPIO_GP_5_1, NULL);
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gpio_direction_output(GPIO_GP_5_2, 1); /* power on */
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gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */
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/* SDHI1/SDHI2 eMMC */
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gpio_request(GPIO_GFN_SD1_DAT0, NULL);
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gpio_request(GPIO_GFN_SD1_DAT1, NULL);
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gpio_request(GPIO_GFN_SD1_DAT2, NULL);
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gpio_request(GPIO_GFN_SD1_DAT3, NULL);
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gpio_request(GPIO_GFN_SD2_DAT0, NULL);
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gpio_request(GPIO_GFN_SD2_DAT1, NULL);
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gpio_request(GPIO_GFN_SD2_DAT2, NULL);
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gpio_request(GPIO_GFN_SD2_DAT3, NULL);
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gpio_request(GPIO_GFN_SD2_CLK, NULL);
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#if defined(CONFIG_R8A7795)
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gpio_request(GPIO_GFN_SD2_CMD, NULL);
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#elif defined(CONFIG_R8A7796)
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gpio_request(GPIO_FN_SD2_CMD, NULL);
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#else
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#error Only R8A7795 and R87796 is supported
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#endif
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gpio_request(GPIO_GP_5_3, NULL);
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gpio_request(GPIO_GP_5_9, NULL);
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gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */
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gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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#if (CONFIG_NR_DRAM_BANKS >= 2)
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gd->ram_size += PHYS_SDRAM_2_SIZE;
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#endif
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#if (CONFIG_NR_DRAM_BANKS >= 3)
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gd->ram_size += PHYS_SDRAM_3_SIZE;
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#endif
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#if (CONFIG_NR_DRAM_BANKS >= 4)
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gd->ram_size += PHYS_SDRAM_4_SIZE;
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#endif
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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#if (CONFIG_NR_DRAM_BANKS >= 2)
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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#endif
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#if (CONFIG_NR_DRAM_BANKS >= 3)
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gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
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gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
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#endif
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#if (CONFIG_NR_DRAM_BANKS >= 4)
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gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
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gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
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#endif
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return 0;
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}
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const struct rmobile_sysinfo sysinfo = {
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CONFIG_RCAR_BOARD_STRING
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};
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