upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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557 lines
15 KiB
557 lines
15 KiB
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* Tegra20 pin multiplexing functions */
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch/pinmux.h>
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/*
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* This defines the order of the pin mux control bits in the registers. For
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* some reason there is no correspendence between the tristate, pin mux and
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* pullup/pulldown registers.
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*/
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enum pmux_ctlid {
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/* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */
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MUXCTL_UAA,
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MUXCTL_UAB,
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MUXCTL_UAC,
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MUXCTL_UAD,
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MUXCTL_UDA,
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MUXCTL_RESERVED5,
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MUXCTL_ATE,
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MUXCTL_RM,
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MUXCTL_ATB,
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MUXCTL_RESERVED9,
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MUXCTL_ATD,
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MUXCTL_ATC,
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MUXCTL_ATA,
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MUXCTL_KBCF,
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MUXCTL_KBCE,
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MUXCTL_SDMMC1,
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/* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */
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MUXCTL_GMA,
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MUXCTL_GMC,
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MUXCTL_HDINT,
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MUXCTL_SLXA,
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MUXCTL_OWC,
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MUXCTL_SLXC,
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MUXCTL_SLXD,
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MUXCTL_SLXK,
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MUXCTL_UCA,
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MUXCTL_UCB,
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MUXCTL_DTA,
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MUXCTL_DTB,
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MUXCTL_RESERVED28,
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MUXCTL_DTC,
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MUXCTL_DTD,
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MUXCTL_DTE,
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/* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */
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MUXCTL_DDC,
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MUXCTL_CDEV1,
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MUXCTL_CDEV2,
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MUXCTL_CSUS,
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MUXCTL_I2CP,
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MUXCTL_KBCA,
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MUXCTL_KBCB,
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MUXCTL_KBCC,
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MUXCTL_IRTX,
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MUXCTL_IRRX,
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MUXCTL_DAP1,
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MUXCTL_DAP2,
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MUXCTL_DAP3,
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MUXCTL_DAP4,
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MUXCTL_GMB,
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MUXCTL_GMD,
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/* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */
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MUXCTL_GME,
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MUXCTL_GPV,
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MUXCTL_GPU,
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MUXCTL_SPDO,
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MUXCTL_SPDI,
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MUXCTL_SDB,
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MUXCTL_SDC,
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MUXCTL_SDD,
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MUXCTL_SPIH,
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MUXCTL_SPIG,
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MUXCTL_SPIF,
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MUXCTL_SPIE,
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MUXCTL_SPID,
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MUXCTL_SPIC,
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MUXCTL_SPIB,
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MUXCTL_SPIA,
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/* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */
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MUXCTL_LPW0,
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MUXCTL_LPW1,
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MUXCTL_LPW2,
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MUXCTL_LSDI,
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MUXCTL_LSDA,
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MUXCTL_LSPI,
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MUXCTL_LCSN,
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MUXCTL_LDC,
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MUXCTL_LSCK,
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MUXCTL_LSC0,
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MUXCTL_LSC1,
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MUXCTL_LHS,
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MUXCTL_LVS,
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MUXCTL_LM0,
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MUXCTL_LM1,
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MUXCTL_LVP0,
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/* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */
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MUXCTL_LD0,
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MUXCTL_LD1,
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MUXCTL_LD2,
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MUXCTL_LD3,
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MUXCTL_LD4,
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MUXCTL_LD5,
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MUXCTL_LD6,
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MUXCTL_LD7,
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MUXCTL_LD8,
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MUXCTL_LD9,
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MUXCTL_LD10,
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MUXCTL_LD11,
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MUXCTL_LD12,
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MUXCTL_LD13,
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MUXCTL_LD14,
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MUXCTL_LD15,
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/* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */
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MUXCTL_LD16,
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MUXCTL_LD17,
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MUXCTL_LHP1,
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MUXCTL_LHP2,
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MUXCTL_LVP1,
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MUXCTL_LHP0,
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MUXCTL_RESERVED102,
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MUXCTL_LPP,
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MUXCTL_LDI,
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MUXCTL_PMC,
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MUXCTL_CRTP,
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MUXCTL_PTA,
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MUXCTL_RESERVED108,
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MUXCTL_KBCD,
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MUXCTL_GPU7,
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MUXCTL_DTF,
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MUXCTL_NONE = -1,
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};
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/*
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* And this defines the order of the pullup/pulldown controls which are again
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* in a different order
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*/
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enum pmux_pullid {
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/* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */
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PUCTL_ATA,
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PUCTL_ATB,
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PUCTL_ATC,
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PUCTL_ATD,
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PUCTL_ATE,
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PUCTL_DAP1,
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PUCTL_DAP2,
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PUCTL_DAP3,
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PUCTL_DAP4,
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PUCTL_DTA,
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PUCTL_DTB,
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PUCTL_DTC,
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PUCTL_DTD,
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PUCTL_DTE,
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PUCTL_DTF,
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PUCTL_GPV,
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/* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */
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PUCTL_RM,
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PUCTL_I2CP,
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PUCTL_PTA,
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PUCTL_GPU7,
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PUCTL_KBCA,
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PUCTL_KBCB,
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PUCTL_KBCC,
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PUCTL_KBCD,
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PUCTL_SPDI,
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PUCTL_SPDO,
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PUCTL_GPSLXAU,
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PUCTL_CRTP,
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PUCTL_SLXC,
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PUCTL_SLXD,
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PUCTL_SLXK,
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/* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */
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PUCTL_CDEV1,
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PUCTL_CDEV2,
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PUCTL_SPIA,
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PUCTL_SPIB,
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PUCTL_SPIC,
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PUCTL_SPID,
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PUCTL_SPIE,
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PUCTL_SPIF,
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PUCTL_SPIG,
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PUCTL_SPIH,
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PUCTL_IRTX,
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PUCTL_IRRX,
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PUCTL_GME,
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PUCTL_RESERVED45,
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PUCTL_XM2D,
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PUCTL_XM2C,
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/* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */
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PUCTL_UAA,
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PUCTL_UAB,
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PUCTL_UAC,
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PUCTL_UAD,
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PUCTL_UCA,
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PUCTL_UCB,
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PUCTL_LD17,
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PUCTL_LD19_18,
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PUCTL_LD21_20,
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PUCTL_LD23_22,
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PUCTL_LS,
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PUCTL_LC,
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PUCTL_CSUS,
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PUCTL_DDRC,
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PUCTL_SDC,
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PUCTL_SDD,
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/* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */
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PUCTL_KBCF,
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PUCTL_KBCE,
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PUCTL_PMCA,
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PUCTL_PMCB,
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PUCTL_PMCC,
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PUCTL_PMCD,
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PUCTL_PMCE,
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PUCTL_CK32,
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PUCTL_UDA,
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PUCTL_SDMMC1,
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PUCTL_GMA,
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PUCTL_GMB,
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PUCTL_GMC,
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PUCTL_GMD,
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PUCTL_DDC,
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PUCTL_OWC,
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PUCTL_NONE = -1
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};
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struct tegra_pingroup_desc {
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const char *name;
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enum pmux_func funcs[4];
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enum pmux_func func_safe;
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enum pmux_vddio vddio;
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enum pmux_ctlid ctl_id;
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enum pmux_pullid pull_id;
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};
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/* Converts a pmux_pingrp number to a tristate register: 0=A, 1=B, 2=C, 3=D */
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#define TRISTATE_REG(pmux_pingrp) ((pmux_pingrp) >> 5)
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/* Mask value for a tristate (within TRISTATE_REG(id)) */
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#define TRISTATE_MASK(pmux_pingrp) (1 << ((pmux_pingrp) & 0x1f))
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/* Converts a PUCTL id to a pull register: 0=A, 1=B...4=E */
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#define PULL_REG(pmux_pullid) ((pmux_pullid) >> 4)
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/* Converts a PUCTL id to a shift position */
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#define PULL_SHIFT(pmux_pullid) ((pmux_pullid << 1) & 0x1f)
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/* Converts a MUXCTL id to a ctl register: 0=A, 1=B...6=G */
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#define MUXCTL_REG(pmux_ctlid) ((pmux_ctlid) >> 4)
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/* Converts a MUXCTL id to a shift position */
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#define MUXCTL_SHIFT(pmux_ctlid) ((pmux_ctlid << 1) & 0x1f)
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/* Convenient macro for defining pin group properties */
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#define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd) \
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{ \
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.vddio = PMUX_VDDIO_ ## vdd, \
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.funcs = { \
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PMUX_FUNC_ ## f0, \
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PMUX_FUNC_ ## f1, \
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PMUX_FUNC_ ## f2, \
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PMUX_FUNC_ ## f3, \
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}, \
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.func_safe = PMUX_FUNC_ ## f_safe, \
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.ctl_id = mux, \
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.pull_id = pupd \
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}
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/* A normal pin group where the mux name and pull-up name match */
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#define PIN(pg_name, vdd, f0, f1, f2, f3, f_safe) \
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PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
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MUXCTL_ ## pg_name, PUCTL_ ## pg_name)
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/* A pin group where the pull-up name doesn't have a 1-1 mapping */
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#define PINP(pg_name, vdd, f0, f1, f2, f3, f_safe, pupd) \
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PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
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MUXCTL_ ## pg_name, PUCTL_ ## pupd)
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/* A pin group number which is not used */
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#define PIN_RESERVED \
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PIN(NONE, NONE, NONE, NONE, NONE, NONE, NONE)
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const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
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PIN(ATA, NAND, IDE, NAND, GMI, RSVD, IDE),
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PIN(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE),
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PIN(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE),
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PIN(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE),
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PIN(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC),
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PIN(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC),
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PIN(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK,
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PLLC_OUT1),
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PIN(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1),
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PIN(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2),
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PIN(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3),
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PIN(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4),
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PIN(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4),
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PIN(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1),
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PIN(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1),
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PIN(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1),
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PIN(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1),
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PINP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4,
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GPSLXAU),
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PIN(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE),
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PIN(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4),
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PIN(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
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PIN(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
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PIN(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC),
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PIN(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC),
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PINP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, NONE),
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PIN(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4),
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PIN(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4),
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PIN(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC),
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PIN(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC),
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PIN(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3),
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PIN(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4),
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PIN(SDMMC1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2),
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PIN(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR),
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PIN(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI),
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PIN(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC),
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PIN(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM),
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PIN_RESERVED,
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PINP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, CRTP),
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PIN(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
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PIN(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
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PIN(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE),
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PIN(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
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PIN(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
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PIN(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
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PIN(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
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PIN(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
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PIN(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
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PIN(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
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PIN(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4),
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PIN(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
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PIN(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
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PIN(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS),
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PIN(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS),
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PIN(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4),
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PIN(UAD, UART, UARTB, SPDIF, UARTA, SPI4, SPDIF),
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PIN(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4),
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PIN(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4),
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PIN_RESERVED,
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PIN(ATE, NAND, IDE, NAND, GMI, RSVD, IDE),
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PIN(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC),
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PIN_RESERVED,
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PIN_RESERVED,
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PIN(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI),
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PIN(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI),
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PIN(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4),
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/* 64 */
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PINP(LD0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
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PINP(LD1, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
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PINP(LD2, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
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PINP(LD3, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
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PINP(LD4, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
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PINP(LD5, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
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PINP(LD6, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
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PINP(LD7, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
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PINP(LD8, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
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PINP(LD9, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
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PINP(LD10, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
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PINP(LD11, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
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PINP(LD12, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
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PINP(LD13, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
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PINP(LD14, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
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PINP(LD15, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
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PINP(LD16, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
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PINP(LD17, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD17),
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PINP(LHP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
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PINP(LHP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
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PINP(LHP2, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
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PINP(LVP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LC),
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PINP(LVP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
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PINP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI , LC),
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PINP(LM0, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LC),
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PINP(LM1, LCD, DISPA, DISPB, RSVD, CRT, RSVD3, LC),
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PINP(LVS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
|
|
PINP(LSC0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
|
|
PINP(LSC1, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
|
|
PINP(LSCK, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
|
|
PINP(LDC, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
|
|
PINP(LCSN, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LS),
|
|
|
|
/* 96 */
|
|
PINP(LSPI, LCD, DISPA, DISPB, XIO, HDMI, DISPA, LC),
|
|
PINP(LSDA, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
|
|
PINP(LSDI, LCD, DISPA, DISPB, SPI3, RSVD, DISPA, LS),
|
|
PINP(LPW0, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
|
|
PINP(LPW1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
|
|
PINP(LPW2, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
|
|
PINP(LDI, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
|
|
PINP(LHS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
|
|
|
|
PINP(LPP, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
|
|
PIN_RESERVED,
|
|
PIN(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC),
|
|
PIN(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK),
|
|
PIN(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4),
|
|
PIN(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2),
|
|
PIN(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD),
|
|
PINP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, NONE),
|
|
|
|
/* these pin groups only have pullup and pull down control */
|
|
PINALL(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
|
|
PUCTL_NONE),
|
|
PINALL(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
|
|
PUCTL_NONE),
|
|
PINALL(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
|
|
PUCTL_NONE),
|
|
PINALL(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
|
|
PUCTL_NONE),
|
|
PINALL(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
|
|
PUCTL_NONE),
|
|
PINALL(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
|
|
PUCTL_NONE),
|
|
PINALL(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
|
|
PUCTL_NONE),
|
|
PINALL(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
|
|
PUCTL_NONE),
|
|
PINALL(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
|
|
PUCTL_NONE),
|
|
};
|
|
|
|
void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
|
|
{
|
|
struct pmux_tri_ctlr *pmt =
|
|
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
|
|
u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)];
|
|
u32 reg;
|
|
|
|
reg = readl(tri);
|
|
if (enable)
|
|
reg |= TRISTATE_MASK(pin);
|
|
else
|
|
reg &= ~TRISTATE_MASK(pin);
|
|
writel(reg, tri);
|
|
}
|
|
|
|
void pinmux_tristate_enable(enum pmux_pingrp pin)
|
|
{
|
|
pinmux_set_tristate(pin, 1);
|
|
}
|
|
|
|
void pinmux_tristate_disable(enum pmux_pingrp pin)
|
|
{
|
|
pinmux_set_tristate(pin, 0);
|
|
}
|
|
|
|
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
|
|
{
|
|
struct pmux_tri_ctlr *pmt =
|
|
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
|
|
enum pmux_pullid pull_id = tegra_soc_pingroups[pin].pull_id;
|
|
u32 *pull = &pmt->pmt_pull[PULL_REG(pull_id)];
|
|
u32 mask_bit;
|
|
u32 reg;
|
|
mask_bit = PULL_SHIFT(pull_id);
|
|
|
|
reg = readl(pull);
|
|
reg &= ~(0x3 << mask_bit);
|
|
reg |= pupd << mask_bit;
|
|
writel(reg, pull);
|
|
}
|
|
|
|
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
|
|
{
|
|
struct pmux_tri_ctlr *pmt =
|
|
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
|
|
enum pmux_ctlid mux_id = tegra_soc_pingroups[pin].ctl_id;
|
|
u32 *muxctl = &pmt->pmt_ctl[MUXCTL_REG(mux_id)];
|
|
u32 mask_bit;
|
|
int i, mux = -1;
|
|
u32 reg;
|
|
|
|
assert(pmux_func_isvalid(func));
|
|
|
|
/* Handle special values */
|
|
if (func >= PMUX_FUNC_RSVD1) {
|
|
mux = (func - PMUX_FUNC_RSVD1) & 0x3;
|
|
} else {
|
|
/* Search for the appropriate function */
|
|
for (i = 0; i < 4; i++) {
|
|
if (tegra_soc_pingroups[pin].funcs[i] == func) {
|
|
mux = i;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
assert(mux != -1);
|
|
|
|
mask_bit = MUXCTL_SHIFT(mux_id);
|
|
reg = readl(muxctl);
|
|
reg &= ~(0x3 << mask_bit);
|
|
reg |= mux << mask_bit;
|
|
writel(reg, muxctl);
|
|
}
|
|
|
|
void pinmux_config_pingroup(const struct pingroup_config *config)
|
|
{
|
|
enum pmux_pingrp pin = config->pingroup;
|
|
|
|
pinmux_set_func(pin, config->func);
|
|
pinmux_set_pullupdown(pin, config->pull);
|
|
pinmux_set_tristate(pin, config->tristate);
|
|
}
|
|
|
|
void pinmux_config_table(const struct pingroup_config *config, int len)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < len; i++)
|
|
pinmux_config_pingroup(&config[i]);
|
|
}
|
|
|