upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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144 lines
3.8 KiB
144 lines
3.8 KiB
/*
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* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
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*
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* Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/arch/ep93xx.h>
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#define SDRAM_BASE_ADDR PHYS_SDRAM_1
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#ifdef CONFIG_EDB93XX_SDCS0
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#define SDRAM_DEVCFG_REG devcfg0
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#elif defined(CONFIG_EDB93XX_SDCS3)
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#define SDRAM_DEVCFG_REG devcfg3
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#else
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#error "SDRAM bank configuration"
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#endif
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#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
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defined(CONFIG_EDB9302A)
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/*
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* 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
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*
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* CLK cycle time min:
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* @ CAS latency = 3: 7.5ns
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* @ CAS latency = 2: 10ns
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* We're running at 66MHz (15ns cycle time) external bus speed (HCLK),
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* so it's safe to use CAS latency = 2
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*
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* RAS-to-CAS delay min:
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* 20ns
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* At 15ns cycle time, we use RAS-to-CAS delay = 2
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*
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* SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear
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* as four blocks of 8MB size, instead of eight blocks of 4MB size:
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*
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* EDB9301/EDB9302:
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*
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* 0x00000000 - 0x007fffff
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* 0x01000000 - 0x017fffff
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* 0x04000000 - 0x047fffff
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* 0x05000000 - 0x057fffff
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*
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*
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* EDB9302a:
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*
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* 0xc0000000 - 0xc07fffff
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* 0xc1000000 - 0xc17fffff
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* 0xc4000000 - 0xc47fffff
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* 0xc5000000 - 0xc57fffff
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*
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* BANKCOUNT = 1: This is a device with four banks
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*/
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#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \
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SDRAM_DEVCFG_SROMLL | \
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SDRAM_DEVCFG_CASLAT_2 | \
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SDRAM_DEVCFG_RASTOCAS_2 | \
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SDRAM_DEVCFG_EXTBUSWIDTH)
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/*
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* 16 bit ext. bus
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*
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* A[22:09] is output as SYA[13:0]
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* CAS latency: 2
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* Burst type: sequential
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* Burst length: 8 (required for 16 bit ext. bus)
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* SYA[13:0] = 0x0023
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*/
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#define SDRAM_MODE_REG_VAL 0x4600
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#define SDRAM_BANK_SEL_0 0x00000000 /* A[22:21] = b00 */
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#define SDRAM_BANK_SEL_1 0x00200000 /* A[22:21] = b01 */
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#define SDRAM_BANK_SEL_2 0x00400000 /* A[22:21] = b10 */
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#define SDRAM_BANK_SEL_3 0x00600000 /* A[22:21] = b11 */
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#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \
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defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) || \
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defined(CONFIG_EDB9315A)
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/*
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* 2x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
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*
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* CLK cycle time min:
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* @ CAS latency = 3: 7.5ns
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* @ CAS latency = 2: 10ns
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* We're running at 100MHz (10ns cycle time) external bus speed (HCLK),
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* so it's safe to use CAS latency = 2
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*
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* RAS-to-CAS delay min:
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* 20ns
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* At 10ns cycle time, we use RAS-to-CAS delay = 2
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*
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* EDB9307, EDB9312, EDB9315:
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*
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* 0x00000000 - 0x01ffffff
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* 0x04000000 - 0x05ffffff
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*
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*
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* EDB9307a, EDB9315a:
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*
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* 0xc0000000 - 0xc1ffffff
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* 0xc4000000 - 0xc5ffffff
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*/
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#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \
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SDRAM_DEVCFG_SROMLL | \
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SDRAM_DEVCFG_CASLAT_2 | \
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SDRAM_DEVCFG_RASTOCAS_2)
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/*
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* 32 bit ext. bus
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*
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* A[23:10] is output as SYA[13:0]
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* CAS latency: 2
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* Burst type: sequential
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* Burst length: 4
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* SYA[13:0] = 0x0022
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*/
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#define SDRAM_MODE_REG_VAL 0x8800
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#define SDRAM_BANK_SEL_0 0x00000000 /* A[23:22] = b00 */
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#define SDRAM_BANK_SEL_1 0x00400000 /* A[23:22] = b01 */
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#define SDRAM_BANK_SEL_2 0x00800000 /* A[23:22] = b10 */
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#define SDRAM_BANK_SEL_3 0x00c00000 /* A[23:22] = b11 */
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#endif
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