upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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118 lines
2.4 KiB
118 lines
2.4 KiB
/*
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* (C) Copyright 2008 - 2013 Tensilica Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/global_data.h>
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#include <linux/stringify.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if XCHAL_HAVE_CCOUNT
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static ulong get_ccount(void)
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{
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ulong ccount;
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asm volatile ("rsr %0,"__stringify(CCOUNT) : "=a" (ccount));
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return ccount;
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}
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#else
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static ulong fake_ccount;
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#define get_ccount() fake_ccount
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#endif
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static void delay_cycles(unsigned cycles)
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{
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#if XCHAL_HAVE_CCOUNT
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unsigned expiry = get_ccount() + cycles;
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while ((signed)(expiry - get_ccount()) > 0)
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;
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#else
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#warning "Without Xtensa timer option, timing will not be accurate."
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/*
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* Approximate the cycle count by a loop iteration count.
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* This is highly dependent on config and optimization.
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*/
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volatile unsigned i;
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for (i = cycles >> 4U; i > 0; --i)
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;
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fake_ccount += cycles;
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#endif
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}
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/*
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* Delay (busy-wait) for a number of microseconds.
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*/
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void __udelay(unsigned long usec)
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{
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ulong lo, hi, i;
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ulong mhz = CONFIG_SYS_CLK_FREQ / 1000000;
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/* Scale to support full 32-bit usec range */
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lo = usec & ((1<<22)-1);
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hi = usec >> 22UL;
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for (i = 0; i < hi; ++i)
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delay_cycles(mhz << 22);
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delay_cycles(mhz * lo);
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}
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/*
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* Return the elapsed time (ticks) since 'base'.
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*/
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ulong get_timer(ulong base)
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{
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/* Don't tie up a timer; use cycle counter if available (or fake it) */
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#if XCHAL_HAVE_CCOUNT
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register ulong ccount;
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__asm__ volatile ("rsr %0, CCOUNT" : "=a"(ccount));
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return ccount / (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - base;
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#else
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/*
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* Add at least the overhead of this call (in cycles).
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* Avoids hanging in case caller doesn't use udelay().
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* Note that functions that don't call udelay() (such as
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* the "sleep" command) will not get a significant delay
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* because there is no time reference.
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*/
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fake_ccount += 20;
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return fake_ccount / (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - base;
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#endif
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}
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/*
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* This function is derived from ARM/PowerPC code (read timebase as long long).
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* On Xtensa it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* This function is derived from ARM/PowerPC code (timebase clock frequency).
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* On Xtensa it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return CONFIG_SYS_HZ;
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}
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#if XCHAL_HAVE_CCOUNT
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unsigned long timer_get_us(void)
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{
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unsigned long ccount;
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__asm__ volatile ("rsr %0, CCOUNT" : "=a"(ccount));
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return ccount / (CONFIG_SYS_CLK_FREQ / 1000000);
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}
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#endif
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