upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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64 lines
2.3 KiB
64 lines
2.3 KiB
#ifndef _405gp_i2c_h_
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#define _405gp_i2c_h_
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#define I2C_REGISTERS_BASE_ADDRESS 0xEF600500
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#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
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#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
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#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
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#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
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#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
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#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
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#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS)
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#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
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#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
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#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
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#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
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#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
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#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
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#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
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#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
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/* MDCNTL Register Bit definition */
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#define IIC_MDCNTL_HSCL 0x01
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#define IIC_MDCNTL_EUBS 0x02
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#define IIC_MDCNTL_EINT 0x04
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#define IIC_MDCNTL_ESM 0x08
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#define IIC_MDCNTL_FSM 0x10
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#define IIC_MDCNTL_EGC 0x20
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#define IIC_MDCNTL_FMDB 0x40
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#define IIC_MDCNTL_FSDB 0x80
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/* CNTL Register Bit definition */
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#define IIC_CNTL_PT 0x01
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#define IIC_CNTL_READ 0x02
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#define IIC_CNTL_CHT 0x04
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#define IIC_CNTL_RPST 0x08
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/* bit 2/3 for Transfer count*/
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#define IIC_CNTL_AMD 0x40
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#define IIC_CNTL_HMT 0x80
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/* STS Register Bit definition */
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#define IIC_STS_PT 0X01
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#define IIC_STS_IRQA 0x02
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#define IIC_STS_ERR 0X04
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#define IIC_STS_SCMP 0x08
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#define IIC_STS_MDBF 0x10
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#define IIC_STS_MDBS 0X20
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#define IIC_STS_SLPR 0x40
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#define IIC_STS_SSS 0x80
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/* EXTSTS Register Bit definition */
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#define IIC_EXTSTS_XFRA 0X01
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#define IIC_EXTSTS_ICT 0X02
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#define IIC_EXTSTS_LA 0X04
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/* XTCNTLSS Register Bit definition */
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#define IIC_XTCNTLSS_SRST 0x01
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#define IIC_XTCNTLSS_EPI 0x02
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#define IIC_XTCNTLSS_SDBF 0x04
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#define IIC_XTCNTLSS_SBDD 0x08
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#define IIC_XTCNTLSS_SWS 0x10
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#define IIC_XTCNTLSS_SWC 0x20
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#define IIC_XTCNTLSS_SRS 0x40
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#define IIC_XTCNTLSS_SRC 0x80
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#endif
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