upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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477 lines
18 KiB
477 lines
18 KiB
/*
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* (C) Copyright 2001-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Modified during 2001 by
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* Advanced Communications Technologies (Australia) Pty. Ltd.
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* Howard Walker, Tuong Vu-Dinh
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*
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* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
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* Added support for the 16M dram simm on the 8260ads boards
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*
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* (C) Copyright 2003 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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* Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc8260.h>
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#include <asm/m8260_pci.h>
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#include <i2c.h>
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#include <spd.h>
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#include <miiphy.h>
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
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/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
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/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
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/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
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/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
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/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
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/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
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/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
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/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
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/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
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/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
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/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
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/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
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/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
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/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
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/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
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/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
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/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
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/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
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/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
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/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
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/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
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/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
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/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
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/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
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/* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
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/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
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/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
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/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
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/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
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/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
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/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
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},
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/* Port B configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
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/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
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/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
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/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
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/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
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/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
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/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
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/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
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/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
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/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
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/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
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/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
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/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
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/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
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/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
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/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
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/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
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/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
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/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
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/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
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/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
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/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
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/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
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/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
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/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
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/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
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/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
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/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
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/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
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/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
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/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
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/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
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/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
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/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
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/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
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/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
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/* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
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/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
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/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
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/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
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/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
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/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */
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/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */
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/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
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/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
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/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
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/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
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/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
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/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
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/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
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/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
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/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
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},
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
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/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
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/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
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/* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
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/* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
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/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
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/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
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/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
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/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
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/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
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/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
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/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
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/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
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/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
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/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
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/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
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/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
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/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
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/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
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/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
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/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
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/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
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/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
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/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
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/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
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/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
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/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
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/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
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/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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}
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};
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void reset_phy (void)
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{
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vu_long *bcsr = (vu_long *)CFG_BCSR;
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/* reset the FEC port */
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bcsr[1] &= ~FETH1_RST;
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udelay(2);
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bcsr[1] |= FETH1_RST;
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udelay(1000);
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#ifdef CONFIG_MII
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#if CONFIG_ADSTYPE == CFG_PQ2FADS
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/*
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* Do not bypass Rx/Tx (de)scrambler (fix configuration error)
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* Enable autonegotiation.
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*/
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miiphy_write(0, 16, 0x610);
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miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
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#else
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/*
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* Ethernet PHY is configured (by means of configuration pins)
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* to work at 10Mb/s only. We reconfigure it using MII
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* to advertise all capabilities, including 100Mb/s, and
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* restart autonegotiation.
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*/
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miiphy_write(0, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
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miiphy_write(0, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */
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miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
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#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
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#endif /* CONFIG_MII */
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}
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int board_early_init_f (void)
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{
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vu_long *bcsr = (vu_long *)CFG_BCSR;
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bcsr[1] = ~FETHIEN1 & ~RS232EN_1;
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#if CONFIG_ADSTYPE != CFG_8260ADS /* PCI mode can be selected */
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#if CONFIG_ADSTYPE == CFG_PQ2FADS
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if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
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#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
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immap->im_siu_conf.sc_siumcr =
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(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
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| SIUMCR_LBPC01;
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}
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#endif /* CONFIG_ADSTYPE != CFG_8260ADS */
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return 0;
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}
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#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
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long int initdram (int board_type)
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{
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#if CONFIG_ADSTYPE == CFG_PQ2FADS
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long int msize = 32;
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#else
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long int msize = 16;
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#endif
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#ifndef CFG_RAMBOOT
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8260_t *memctl = &immap->im_memctl;
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volatile uchar *ramaddr, c = 0xff;
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uint or;
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uint psdmr;
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uint psrt;
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int i;
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immap->im_siu_conf.sc_ppc_acr = 0x00000002;
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immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
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immap->im_siu_conf.sc_tescr1 = 0x00004000;
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memctl->memc_mptpr = CFG_MPTPR;
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#ifdef CFG_LSDRAM_BASE
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/*
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Initialise local bus SDRAM only if the pins
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are configured as local bus pins and not as PCI.
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The configuration is determined by the HRCW.
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*/
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if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
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memctl->memc_lsrt = CFG_LSRT;
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#if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */
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memctl->memc_or3 = 0xFF803280;
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memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861;
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#else /* CS4 */
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memctl->memc_or4 = 0xFFC01480;
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memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
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#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
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memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
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ramaddr = (uchar *) CFG_LSDRAM_BASE;
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*ramaddr = c;
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memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
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for (i = 0; i < 8; i++)
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*ramaddr = c;
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memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
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*ramaddr = c;
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memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
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}
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#endif /* CFG_LSDRAM_BASE */
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/* Init 60x bus SDRAM */
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#ifdef CONFIG_SPD_EEPROM
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{
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spd_eeprom_t spd;
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uint pbi, bsel, rowst, lsb, tmp;
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i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
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/* Bank-based interleaving is not supported for physical bank
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sizes greater than 128MB which is encoded as 0x20 in SPD
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*/
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pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
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msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */
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or = ~(msize - 1) << 20; /* SDAM */
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switch (spd.nbanks) { /* BPD */
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case 2:
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bsel = 1;
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break;
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case 4:
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bsel = 2;
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or |= 0x00002000;
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break;
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case 8:
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bsel = 3;
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or |= 0x00004000;
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break;
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}
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lsb = 3; /* For 64-bit port, lsb is 3 bits */
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if (pbi) { /* Bus partition depends on interleaving */
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rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
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or |= (rowst << 9); /* ROWST */
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} else {
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rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
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or |= ((rowst * 2 - 12) << 9); /* ROWST */
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}
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or |= ((spd.nrow_addr - 9) << 6); /* NUMR */
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psdmr = (pbi << 31); /* PBI */
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/* Bus multiplexing parameters */
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tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */
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psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */
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psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */
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tmp = (31 - lsb - 10) - tmp;
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/* Pin connected to SDA10 is (31 - lsb - 10).
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rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
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so (rowst + tmp) alternates with AP.
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*/
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|
if (pbi) /* Table 10-7 */
|
|
psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */
|
|
else
|
|
psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */
|
|
|
|
/* SDRAM device-specific parameters */
|
|
tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */
|
|
switch (tmp) { /* RFRC */
|
|
case 1:
|
|
case 2:
|
|
psdmr |= (1 << 15);
|
|
break;
|
|
case 3:
|
|
case 4:
|
|
case 5:
|
|
case 6:
|
|
case 7:
|
|
case 8:
|
|
psdmr |= ((tmp - 2) << 15);
|
|
break;
|
|
default:
|
|
psdmr |= (7 << 15);
|
|
}
|
|
psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */
|
|
psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */
|
|
/* BL=0 because for 64-bit SDRAM burst length must be 4 */
|
|
/* LDOTOPRE ??? */
|
|
for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
|
|
tmp >>= 1;
|
|
switch (i) { /* WRC */
|
|
case 0:
|
|
case 1:
|
|
psdmr |= (1 << 4);
|
|
break;
|
|
case 2:
|
|
case 3:
|
|
psdmr |= (i << 4);
|
|
break;
|
|
}
|
|
/* EAMUX=0 - no external address multiplexing */
|
|
/* BUFCMD=0 - no external buffers */
|
|
for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
|
|
tmp >>= 1;
|
|
psdmr |= i; /* CL */
|
|
|
|
switch (spd.refresh & 0x7F) {
|
|
case 1:
|
|
tmp = 3900;
|
|
break;
|
|
case 2:
|
|
tmp = 7800;
|
|
break;
|
|
case 3:
|
|
tmp = 31300;
|
|
break;
|
|
case 4:
|
|
tmp = 62500;
|
|
break;
|
|
case 5:
|
|
tmp = 125000;
|
|
break;
|
|
default:
|
|
tmp = 15625;
|
|
}
|
|
psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
|
|
((memctl->memc_mptpr >> 8) + 1)) - 1;
|
|
#ifdef SPD_DEBUG
|
|
printf ("\nDIMM type: %-18.18s\n", spd.mpart);
|
|
printf ("SPD size: %d\n", spd.info_size);
|
|
printf ("EEPROM size: %d\n", 1 << spd.chip_size);
|
|
printf ("Memory type: %d\n", spd.mem_type);
|
|
printf ("Row addr: %d\n", spd.nrow_addr);
|
|
printf ("Column addr: %d\n", spd.ncol_addr);
|
|
printf ("# of rows: %d\n", spd.nrows);
|
|
printf ("Row density: %d\n", spd.row_dens);
|
|
printf ("# of banks: %d\n", spd.nbanks);
|
|
printf ("Data width: %d\n",
|
|
256 * spd.dataw_msb + spd.dataw_lsb);
|
|
printf ("Chip width: %d\n", spd.primw);
|
|
printf ("Refresh rate: %02X\n", spd.refresh);
|
|
printf ("CAS latencies: %02X\n", spd.cas_lat);
|
|
printf ("Write latencies: %02X\n", spd.write_lat);
|
|
printf ("tRP: %d\n", spd.trp);
|
|
printf ("tRCD: %d\n", spd.trcd);
|
|
|
|
printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
|
|
#endif /* SPD_DEBUG */
|
|
}
|
|
#else /* !CONFIG_SPD_EEPROM */
|
|
or = CFG_OR2;
|
|
psdmr = CFG_PSDMR;
|
|
psrt = CFG_PSRT;
|
|
#endif /* CONFIG_SPD_EEPROM */
|
|
memctl->memc_psrt = psrt;
|
|
memctl->memc_or2 = or;
|
|
memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
|
|
ramaddr = (uchar *) CFG_SDRAM_BASE;
|
|
memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */
|
|
*ramaddr = c;
|
|
memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */
|
|
for (i = 0; i < 8; i++)
|
|
*ramaddr = c;
|
|
|
|
memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */
|
|
*ramaddr = c;
|
|
memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */
|
|
*ramaddr = c;
|
|
#endif /* CFG_RAMBOOT */
|
|
|
|
/* return total 60x bus SDRAM size */
|
|
return (msize * 1024 * 1024);
|
|
}
|
|
|
|
int checkboard (void)
|
|
{
|
|
#if CONFIG_ADSTYPE == CFG_8260ADS
|
|
puts ("Board: Motorola MPC8260ADS\n");
|
|
#elif CONFIG_ADSTYPE == CFG_8266ADS
|
|
puts ("Board: Motorola MPC8266ADS\n");
|
|
#elif CONFIG_ADSTYPE == CFG_PQ2FADS
|
|
puts ("Board: Motorola PQ2FADS-ZU\n");
|
|
#else
|
|
puts ("Board: unknown\n");
|
|
#endif
|
|
return 0;
|
|
}
|
|
|