upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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59 lines
1.7 KiB
59 lines
1.7 KiB
/*
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* Copyright 2008 Extreme Engineering Solutions, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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/*
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* Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
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*/
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unsigned long get_board_sys_clk(ulong dummy)
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{
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#if defined(CONFIG_MPC85xx)
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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#elif defined(CONFIG_MPC86xx)
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immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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#endif
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u32 gpporcr = gur->gpporcr;
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if (gpporcr & 0x10000)
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return 66666666;
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else
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return 50000000;
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}
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#ifdef CONFIG_MPC85xx
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/*
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* Return DDR input clock - synchronous with SYSCLK or 66 MHz
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* Note: 86xx doesn't support asynchronous DDR clk
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*/
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unsigned long get_board_ddr_clk(ulong dummy)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
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if (ddr_ratio == 0x7)
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return get_board_sys_clk(dummy);
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return 66666666;
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}
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#endif
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