upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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77 lines
1.7 KiB
77 lines
1.7 KiB
/*
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* ARC Build Configuration Registers, with encoded hardware config
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*
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* Copyright (C) 2018 Synopsys
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* Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ARC_BCR_H
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#define __ARC_BCR_H
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#ifndef __ASSEMBLY__
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#include <config.h>
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union bcr_di_cache {
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struct {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
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#else
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unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
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#endif
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} fields;
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unsigned int word;
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};
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union bcr_slc_cfg {
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struct {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:24, way:2, lsz:2, sz:4;
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#else
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unsigned int sz:4, lsz:2, way:2, pad:24;
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#endif
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} fields;
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unsigned int word;
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};
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union bcr_generic {
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struct {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:24, ver:8;
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#else
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unsigned int ver:8, pad:24;
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#endif
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} fields;
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unsigned int word;
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};
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union bcr_clust_cfg {
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struct {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
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#else
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unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
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#endif
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} fields;
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unsigned int word;
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};
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union bcr_mmu_4 {
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struct {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
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n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
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#else
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/* DTLB ITLB JES JE JA */
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unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
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pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
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#endif
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} fields;
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unsigned int word;
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __ARC_BCR_H */
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