upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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41 lines
1.1 KiB
41 lines
1.1 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <ahci.h>
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#include <scsi.h>
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/* port register default value */
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#define AHCI_PORT_PHY_1_CFG 0xa003fffe
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#define AHCI_PORT_PHY_2_CFG 0x28183414
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#define AHCI_PORT_PHY_3_CFG 0x0e080e06
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#define AHCI_PORT_PHY_4_CFG 0x064a080b
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#define AHCI_PORT_PHY_5_CFG 0x2aa86470
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#define AHCI_PORT_TRANS_CFG 0x08000029
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#define SATA_ECC_REG_ADDR 0x20220520
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#define SATA_ECC_DISABLE 0x00020000
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int ls1021a_sata_init(void)
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{
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struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR;
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
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out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE);
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#endif
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out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
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out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
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out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
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out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG);
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out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG);
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out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
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ahci_init((void __iomem *)AHCI_BASE_ADDR);
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scsi_scan(false);
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return 0;
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}
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