upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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504 lines
12 KiB
504 lines
12 KiB
/*
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* Copyright 2007 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/immap_fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <tsec.h>
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#include <netdev.h>
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#include "../common/pixis.h"
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#include "../common/sgmii_riser.h"
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int checkboard (void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
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volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
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if ((uint)&gur->porpllsr != 0xe00e0000) {
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printf("immap size error %lx\n",(ulong)&gur->porpllsr);
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}
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printf ("Board: MPC8544DS, System ID: 0x%02x, "
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"System Version: 0x%02x, FPGA Version: 0x%02x\n",
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in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
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in8(PIXIS_BASE + PIXIS_PVER));
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lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
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lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
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ecm->eedr = 0xffffffff; /* Clear ecm errors */
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ecm->eeer = 0xffffffff; /* Enable ecm errors */
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return 0;
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}
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phys_size_t
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initdram(int board_type)
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{
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long dram_size = 0;
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puts("Initializing\n");
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dram_size = fsl_ddr_sdram();
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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puts(" DDR: ");
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return dram_size;
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}
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#ifdef CONFIG_PCI1
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static struct pci_controller pci1_hose;
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#endif
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif
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#ifdef CONFIG_PCIE2
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static struct pci_controller pcie2_hose;
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#endif
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#ifdef CONFIG_PCIE3
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static struct pci_controller pcie3_hose;
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#endif
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extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
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extern void fsl_pci_init(struct pci_controller *hose);
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int first_free_busno=0;
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void
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pci_init_board(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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uint devdisr = gur->devdisr;
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uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
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debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
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devdisr, io_sel, host_agent);
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if (io_sel & 1) {
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
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printf (" eTSEC1 is in sgmii mode.\n");
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
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printf (" eTSEC3 is in sgmii mode.\n");
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}
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#ifdef CONFIG_PCIE3
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
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struct pci_controller *hose = &pcie3_hose;
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int pcie_ep = (host_agent == 1);
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int pcie_configured = io_sel >= 6;
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struct pci_region *r = hose->regions;
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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printf ("\n PCIE3 connected to ULI as %s (base address %x)",
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pcie_ep ? "End Point" : "Root Complex",
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(uint)pci);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
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}
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printf ("\n");
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/* inbound */
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE3_MEM_BUS,
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CONFIG_SYS_PCIE3_MEM_PHYS,
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CONFIG_SYS_PCIE3_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCIE3_IO_BUS,
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CONFIG_SYS_PCIE3_IO_PHYS,
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CONFIG_SYS_PCIE3_IO_SIZE,
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PCI_REGION_IO);
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#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE3_MEM_BUS2,
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CONFIG_SYS_PCIE3_MEM_PHYS2,
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CONFIG_SYS_PCIE3_MEM_SIZE2,
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PCI_REGION_MEM);
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#endif
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hose->region_count = r - hose->regions;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno=hose->last_busno+1;
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printf (" PCIE3 on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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/*
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* Activate ULI1575 legacy chip by performing a fake
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* memory access. Needed to make ULI RTC work.
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*/
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in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
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} else {
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printf (" PCIE3: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
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#endif
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#ifdef CONFIG_PCIE1
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
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struct pci_controller *hose = &pcie1_hose;
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int pcie_ep = (host_agent == 5);
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int pcie_configured = io_sel >= 2;
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struct pci_region *r = hose->regions;
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
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pcie_ep ? "End Point" : "Root Complex",
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(uint)pci);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
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}
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printf ("\n");
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/* inbound */
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_MEM_BUS,
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CONFIG_SYS_PCIE1_MEM_PHYS,
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CONFIG_SYS_PCIE1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_IO_BUS,
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CONFIG_SYS_PCIE1_IO_PHYS,
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CONFIG_SYS_PCIE1_IO_SIZE,
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PCI_REGION_IO);
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#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_MEM_BUS2,
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CONFIG_SYS_PCIE1_MEM_PHYS2,
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CONFIG_SYS_PCIE1_MEM_SIZE2,
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PCI_REGION_MEM);
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#endif
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hose->region_count = r - hose->regions;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno=hose->last_busno+1;
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printf(" PCIE1 on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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} else {
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printf (" PCIE1: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
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#endif
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#ifdef CONFIG_PCIE2
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
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struct pci_controller *hose = &pcie2_hose;
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int pcie_ep = (host_agent == 3);
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int pcie_configured = io_sel >= 4;
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struct pci_region *r = hose->regions;
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
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pcie_ep ? "End Point" : "Root Complex",
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(uint)pci);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
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}
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printf ("\n");
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/* inbound */
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE2_MEM_BUS,
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CONFIG_SYS_PCIE2_MEM_PHYS,
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CONFIG_SYS_PCIE2_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCIE2_IO_BUS,
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CONFIG_SYS_PCIE2_IO_PHYS,
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CONFIG_SYS_PCIE2_IO_SIZE,
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PCI_REGION_IO);
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#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE2_MEM_BUS2,
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CONFIG_SYS_PCIE2_MEM_PHYS2,
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CONFIG_SYS_PCIE2_MEM_SIZE2,
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PCI_REGION_MEM);
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#endif
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hose->region_count = r - hose->regions;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno=hose->last_busno+1;
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printf (" PCIE2 on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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} else {
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printf (" PCIE2: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
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#endif
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#ifdef CONFIG_PCI1
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
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struct pci_controller *hose = &pci1_hose;
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struct pci_region *r = hose->regions;
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uint pci_agent = (host_agent == 6);
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uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
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uint pci_32 = 1;
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uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
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uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
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(pci_32) ? 32 : 64,
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(pci_speed == 33333000) ? "33" :
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(pci_speed == 66666000) ? "66" : "unknown",
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pci_clk_sel ? "sync" : "async",
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pci_agent ? "agent" : "host",
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pci_arb ? "arbiter" : "external-arbiter",
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(uint)pci
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);
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/* inbound */
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCI1_MEM_BUS,
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CONFIG_SYS_PCI1_MEM_PHYS,
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CONFIG_SYS_PCI1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCI1_IO_BUS,
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CONFIG_SYS_PCI1_IO_PHYS,
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CONFIG_SYS_PCI1_IO_SIZE,
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PCI_REGION_IO);
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#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE3_MEM_BUS2,
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CONFIG_SYS_PCIE3_MEM_PHYS2,
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CONFIG_SYS_PCIE3_MEM_SIZE2,
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PCI_REGION_MEM);
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#endif
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hose->region_count = r - hose->regions;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno=hose->last_busno+1;
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printf ("PCI on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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} else {
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printf (" PCI: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
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#endif
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}
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int last_stage_init(void)
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{
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return 0;
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}
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unsigned long
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get_board_sys_clk(ulong dummy)
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{
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u8 i, go_bit, rd_clks;
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ulong val = 0;
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go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
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go_bit &= 0x01;
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rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
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rd_clks &= 0x1C;
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/*
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* Only if both go bit and the SCLK bit in VCFGEN0 are set
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* should we be using the AUX register. Remember, we also set the
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* GO bit to boot from the alternate bank on the on-board flash
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*/
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if (go_bit) {
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if (rd_clks == 0x1c)
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i = in8(PIXIS_BASE + PIXIS_AUX);
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else
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i = in8(PIXIS_BASE + PIXIS_SPD);
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} else {
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i = in8(PIXIS_BASE + PIXIS_SPD);
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}
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i &= 0x07;
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switch (i) {
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case 0:
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val = 33333333;
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break;
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case 1:
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val = 40000000;
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break;
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case 2:
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val = 50000000;
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break;
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case 3:
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val = 66666666;
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break;
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case 4:
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val = 83000000;
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break;
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case 5:
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val = 100000000;
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break;
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case 6:
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val = 133333333;
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break;
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case 7:
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val = 166666666;
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break;
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}
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return val;
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}
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_TSEC_ENET
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struct tsec_info_struct tsec_info[2];
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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int num = 0;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
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tsec_info[num].flags |= TSEC_SGMII;
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num++;
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#endif
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#ifdef CONFIG_TSEC3
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SET_STD_TSEC_INFO(tsec_info[num], 3);
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
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tsec_info[num].flags |= TSEC_SGMII;
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num++;
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#endif
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if (!num) {
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printf("No TSECs initialized\n");
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return 0;
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}
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if (io_sel & 1)
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fsl_sgmii_riser_init(tsec_info, num);
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tsec_eth_init(bis, tsec_info, num);
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#endif
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return pci_eth_init(bis);
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
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struct pci_controller *hose);
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|
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
|
|
|
|
|
|
#ifdef CONFIG_PCI1
|
|
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
|
|
#endif
|
|
#ifdef CONFIG_PCIE2
|
|
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
|
|
#endif
|
|
#ifdef CONFIG_PCIE1
|
|
ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
|
|
#endif
|
|
#ifdef CONFIG_PCIE3
|
|
ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);
|
|
#endif
|
|
#ifdef CONFIG_FSL_SGMII_RISER
|
|
fsl_sgmii_riser_fdt_fixup(blob);
|
|
#endif
|
|
}
|
|
#endif
|
|
|