upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
67 lines
2.0 KiB
67 lines
2.0 KiB
/*
|
|
*
|
|
* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
|
|
*
|
|
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
|
|
*
|
|
* See file CREDITS for list of people who contributed to this
|
|
* project.
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
* MA 02111-1307 USA
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/arch/imx-regs.h>
|
|
#include <asm/arch/clock.h>
|
|
|
|
void mx31_uart1_hw_init(void)
|
|
{
|
|
/* setup pins for UART1 */
|
|
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
|
|
mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
|
|
mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
|
|
mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
|
|
}
|
|
|
|
void mx31_uart2_hw_init(void)
|
|
{
|
|
/* setup pins for UART2 */
|
|
mx31_gpio_mux(MUX_RXD2__UART2_RXD_MUX);
|
|
mx31_gpio_mux(MUX_TXD2__UART2_TXD_MUX);
|
|
mx31_gpio_mux(MUX_RTS2__UART2_RTS_B);
|
|
mx31_gpio_mux(MUX_CTS2__UART2_CTS_B);
|
|
}
|
|
|
|
#ifdef CONFIG_MXC_SPI
|
|
/*
|
|
* Note: putting several spi setups here makes no sense as they may differ
|
|
* at board level (physical pin SS0 of CSPI2 may aswell be used as SS0 of CSPI3)
|
|
*/
|
|
void mx31_spi2_hw_init(void)
|
|
{
|
|
/* SPI2 */
|
|
mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
|
|
mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
|
|
mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
|
|
mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
|
|
mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
|
|
mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
|
|
mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
|
|
|
|
/* start SPI2 clock */
|
|
__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
|
|
}
|
|
#endif
|
|
|