upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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408 lines
11 KiB
408 lines
11 KiB
/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#include <commproc.h>
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#include <command.h>
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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void can_driver_enable (void);
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void can_driver_disable (void);
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int fpga_init(void);
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/* ------------------------------------------------------------------------- */
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#define _NOT_USED_ 0xFFFFFFFF
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const uint sdram_table[] =
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{
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
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0x1FF5FC47, /* last */
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
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/*
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* Burst Read. (Offset 8 in UPMA RAM)
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*/
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0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
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0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPMA RAM)
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*/
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0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPMA RAM)
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*/
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0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
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0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPMA RAM)
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*/
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0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC84, 0xFFFFFC07, /* last */
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_NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPMA RAM)
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*/
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0x7FFFFC07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*
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* Always return 1 (no second DRAM bank since based on TQM8xxL module)
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*/
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int checkboard (void)
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{
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unsigned char *s;
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unsigned char buf[64];
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s = (getenv_r ("serial#", buf, sizeof(buf)) > 0) ? buf : NULL;
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puts ("Board: Siemens CCM");
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if (s) {
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puts (" (");
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for (; *s; ++s) {
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if (*s == ' ')
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break;
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putc (*s);
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}
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putc (')');
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}
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putc ('\n');
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* If Power-On-Reset switch off the Red and Green LED: At reset, the
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* data direction registers are cleared and must therefore be restored.
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*/
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#define RSR_CSRS 0x08000000
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int power_on_reset(void)
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{
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/* Test Reset Status Register */
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return ((volatile immap_t *)CFG_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1;
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}
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#define PB_LED_GREEN 0x10000 /* red LED is on PB.15 */
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#define PB_LED_RED 0x20000 /* red LED is on PB.14 */
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#define PB_LEDS (PB_LED_GREEN | PB_LED_RED);
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static void init_leds (void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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immap->im_cpm.cp_pbpar &= ~PB_LEDS;
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immap->im_cpm.cp_pbodr &= ~PB_LEDS;
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immap->im_cpm.cp_pbdir |= PB_LEDS;
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/* Check stop reset status */
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if (power_on_reset()) {
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immap->im_cpm.cp_pbdat &= ~PB_LEDS;
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}
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}
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size8, size9;
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long int size = 0;
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unsigned long reg;
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upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
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/*
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* Preliminary prescaler for refresh (depends on number of
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* banks): This value is selected for four cycles every 62.4 us
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* with two SDRAM banks or four cycles every 31.2 us with one
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* bank. It will be adjusted after memory sizing.
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*/
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memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
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memctl->memc_mar = 0x00000088;
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/*
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* Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
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* preliminary addresses - these have to be modified after the
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* SDRAM size has been determined.
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*/
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memctl->memc_or2 = CFG_OR2_PRELIM;
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memctl->memc_br2 = CFG_BR2_PRELIM;
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memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
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udelay(200);
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/* perform SDRAM initializsation sequence */
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memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
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udelay(1);
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memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
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udelay(1);
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memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
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udelay (1000);
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/*
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* Check Bank 0 Memory Size for re-configuration
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*
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* try 8 column mode
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*/
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size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
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udelay (1000);
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/*
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* try 9 column mode
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*/
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size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
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if (size8 < size9) { /* leave configuration at 9 columns */
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size = size9;
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/* debug ("SDRAM in 9 column mode: %ld MB\n", size >> 20); */
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} else { /* back to 8 columns */
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size = size8;
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memctl->memc_mamr = CFG_MAMR_8COL;
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udelay(500);
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/* debug ("SDRAM in 8 column mode: %ld MB\n", size >> 20); */
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}
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udelay (1000);
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/*
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* Adjust refresh rate depending on SDRAM type
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* For types > 128 MBit leave it at the current (fast) rate
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*/
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if (size < 0x02000000) {
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/* reduce to 15.6 us (62.4 us / quad) */
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memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
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udelay(1000);
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}
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/*
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* Final mapping
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*/
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memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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/* adjust refresh rate depending on SDRAM type, one bank */
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reg = memctl->memc_mptpr;
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reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
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memctl->memc_mptpr = reg;
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can_driver_enable ();
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init_leds ();
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udelay(10000);
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return (size);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Warning - both the PUMA load mode and the CAN driver use UPM B,
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* so make sure only one of both is active.
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*/
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void can_driver_enable (void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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/* Initialize MBMR */
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memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
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/* Initialize UPMB for CAN: single read */
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memctl->memc_mdr = 0xFFFFC004;
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memctl->memc_mcr = 0x0100 | UPMB;
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memctl->memc_mdr = 0x0FFFD004;
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memctl->memc_mcr = 0x0101 | UPMB;
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memctl->memc_mdr = 0x0FFFC000;
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memctl->memc_mcr = 0x0102 | UPMB;
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memctl->memc_mdr = 0x3FFFC004;
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memctl->memc_mcr = 0x0103 | UPMB;
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memctl->memc_mdr = 0xFFFFDC05;
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memctl->memc_mcr = 0x0104 | UPMB;
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/* Initialize UPMB for CAN: single write */
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memctl->memc_mdr = 0xFFFCC004;
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memctl->memc_mcr = 0x0118 | UPMB;
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memctl->memc_mdr = 0xCFFCD004;
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memctl->memc_mcr = 0x0119 | UPMB;
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memctl->memc_mdr = 0x0FFCC000;
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memctl->memc_mcr = 0x011A | UPMB;
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memctl->memc_mdr = 0x7FFCC004;
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memctl->memc_mcr = 0x011B | UPMB;
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memctl->memc_mdr = 0xFFFDCC05;
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memctl->memc_mcr = 0x011C | UPMB;
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/* Initialize OR3 / BR3 for CAN Bus Controller */
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memctl->memc_or3 = CFG_OR3_CAN;
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memctl->memc_br3 = CFG_BR3_CAN;
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}
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void can_driver_disable (void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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/* Reset OR3 / BR3 to disable CAN Bus Controller */
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memctl->memc_br3 = 0;
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memctl->memc_or3 = 0;
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memctl->memc_mbmr = 0;
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mamr_value, long int *base, long int maxsize)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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memctl->memc_mamr = mamr_value;
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return (get_ram_size(base, maxsize));
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}
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/* ------------------------------------------------------------------------- */
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#define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
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#define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN)
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void reset_phy(void)
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{
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immap_t *immr = (immap_t *)CFG_IMMR;
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ulong value;
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/* Configure all needed port pins for GPIO */
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#if CFG_ETH_MDDIS_VALUE
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immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS;
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#else
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immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET); /* Set low */
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#endif
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immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET); /* GPIO */
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immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET); /* active output */
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immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET; /* output */
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immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
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immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
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value = immr->im_cpm.cp_pbdat;
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/* Assert Powerdown and Reset signals */
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value |= CFG_PB_ETH_POWERDOWN;
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/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
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#if CFG_ETH_CFG1_VALUE
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value |= CFG_PB_ETH_CFG1;
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#else
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value &= ~(CFG_PB_ETH_CFG1);
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#endif
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#if CFG_ETH_CFG2_VALUE
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value |= CFG_PB_ETH_CFG2;
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#else
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value &= ~(CFG_PB_ETH_CFG2);
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#endif
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#if CFG_ETH_CFG3_VALUE
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value |= CFG_PB_ETH_CFG3;
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#else
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value &= ~(CFG_PB_ETH_CFG3);
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#endif
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/* Drive output signals to initial state */
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immr->im_cpm.cp_pbdat = value;
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immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
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udelay (10000);
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/* De-assert Ethernet Powerdown */
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immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
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udelay (10000);
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/* de-assert RESET signal of PHY */
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immr->im_ioport.iop_padat |= CFG_PA_ETH_RESET;
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udelay (1000);
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}
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int misc_init_r (void)
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{
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fpga_init();
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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