upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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365 lines
8.0 KiB
365 lines
8.0 KiB
/*
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* Memory setup for SMDKV310 board based on EXYNOS4210
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*
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* Copyright (C) 2011 Samsung Electronics
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#define SET_MIU
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#define MEM_DLL
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#ifdef CONFIG_CLK_800_330_165
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#define DRAM_CLK_330
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#endif
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#ifdef CONFIG_CLK_1000_200_200
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#define DRAM_CLK_200
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#endif
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#ifdef CONFIG_CLK_1000_330_165
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#define DRAM_CLK_330
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#endif
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#ifdef CONFIG_CLK_1000_400_200
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#define DRAM_CLK_400
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#endif
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.globl mem_ctrl_asm_init
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mem_ctrl_asm_init:
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/*
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* Async bridge configuration at CPU_core:
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* 1: half_sync
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* 0: full_sync
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*/
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ldr r0, =0x10010350
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mov r1, #1
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str r1, [r0]
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#ifdef SET_MIU
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ldr r0, =EXYNOS4_MIU_BASE @0x10600000
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#ifdef CONFIG_MIU_1BIT_INTERLEAVED
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ldr r1, =0x0000000c
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str r1, [r0, #0x400] @MIU_INTLV_CONFIG
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ldr r1, =0x40000000
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str r1, [r0, #0x808] @MIU_INTLV_START_ADDR
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ldr r1, =0xbfffffff
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str r1, [r0, #0x810] @MIU_INTLV_END_ADDR
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ldr r1, =0x00000001
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str r1, [r0, #0x800] @MIU_MAPPING_UPDATE
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#endif
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#ifdef CONFIG_MIU_2BIT_INTERLEAVED
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ldr r1, =0x2000150c
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str r1, [r0, #0x400] @MIU_INTLV_CONFIG
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ldr r1, =0x40000000
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str r1, [r0, #0x808] @MIU_INTLV_START_ADDR
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ldr r1, =0xbfffffff
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str r1, [r0, #0x810] @MIU_INTLV_END_ADDR
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ldr r1, =0x00000001
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str r1, [r0, #0x800] @MIU_MAPPING_UPDATE
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#endif
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#ifdef CONFIG_MIU_LINEAR
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ldr r1, =0x40000000
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str r1, [r0, #0x818] @MIU_SINGLE_MAPPING0_START_ADDR
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ldr r1, =0x7fffffff
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str r1, [r0, #0x820] @MIU_SINGLE_MAPPING0_END_ADDR
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ldr r1, =0x80000000
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str r1, [r0, #0x828] @MIU_SINGLE_MAPPING1_START_ADDR
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ldr r1, =0xbfffffff
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str r1, [r0, #0x830] @MIU_SINGLE_MAPPING1_END_ADDR]
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ldr r1, =0x00000006
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str r1, [r0, #0x800] @MIU_MAPPING_UPDATE
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#endif
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#endif
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/* DREX0 */
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ldr r0, =EXYNOS4_DMC0_BASE @0x10400000
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ldr r1, =0xe0000086
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str r1, [r0, #0x1C] @DMC_PHYCONTROL1
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ldr r1, =0xE3855703
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str r1, [r0, #0x44] @DMC_PHYZQCONTROL
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mov r2, #0x100000
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1: subs r2, r2, #1
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bne 1b
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ldr r1, =0xe000008e
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str r1, [r0, #0x1C] @DMC_PHYCONTROL1
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ldr r1, =0xe0000086
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str r1, [r0, #0x1C] @DMC_PHYCONTROL1
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ldr r1, =0x71101008
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str r1, [r0, #0x18] @DMC_PHYCONTROL0
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ldr r1, =0x7110100A
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str r1, [r0, #0x18] @DMC_PHYCONTROL0
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ldr r1, =0xe0000086
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str r1, [r0, #0x1C] @DMC_PHYCONTROL1
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ldr r1, =0x7110100B
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str r1, [r0, #0x18] @DMC_PHYCONTROL0
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ldr r1, =0x00000000
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str r1, [r0, #0x20] @DMC_PHYCONTROL2
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ldr r1, =0x0FFF301a
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str r1, [r0, #0x00] @DMC_CONCONTROL
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ldr r1, =0x00312640
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str r1, [r0, #0x04] @DMC_MEMCONTROL]
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#ifdef CONFIG_MIU_LINEAR
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ldr r1, =0x40e01323
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str r1, [r0, #0x08] @DMC_MEMCONFIG0
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ldr r1, =0x60e01323
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str r1, [r0, #0x0C] @DMC_MEMCONFIG1
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#else /* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
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ldr r1, =0x20e01323
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str r1, [r0, #0x08] @DMC_MEMCONFIG0
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ldr r1, =0x40e01323
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str r1, [r0, #0x0C] @DMC_MEMCONFIG1
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#endif
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ldr r1, =0xff000000
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str r1, [r0, #0x14] @DMC_PRECHCONFIG
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ldr r1, =0x000000BC
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str r1, [r0, #0x30] @DMC_TIMINGAREF
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#ifdef DRAM_CLK_330
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ldr r1, =0x3545548d
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str r1, [r0, #0x34] @DMC_TIMINGROW
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ldr r1, =0x45430506
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str r1, [r0, #0x38] @DMC_TIMINGDATA
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ldr r1, =0x4439033c
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str r1, [r0, #0x3C] @DMC_TIMINGPOWER
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#endif
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#ifdef DRAM_CLK_400
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ldr r1, =0x4046654f
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str r1, [r0, #0x34] @DMC_TIMINGROW
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ldr r1, =0x56500506
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str r1, [r0, #0x38] @DMC_TIMINGDATA
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ldr r1, =0x5444033d
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str r1, [r0, #0x3C] @DMC_TIMINGPOWER
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#endif
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ldr r1, =0x07000000
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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mov r2, #0x100000
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2: subs r2, r2, #1
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bne 2b
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ldr r1, =0x00020000
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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ldr r1, =0x00030000
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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ldr r1, =0x00010002
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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ldr r1, =0x00000328
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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mov r2, #0x100000
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3: subs r2, r2, #1
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bne 3b
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ldr r1, =0x0a000000
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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mov r2, #0x100000
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4: subs r2, r2, #1
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bne 4b
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ldr r1, =0x07100000
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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mov r2, #0x100000
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5: subs r2, r2, #1
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bne 5b
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ldr r1, =0x00120000
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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ldr r1, =0x00130000
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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ldr r1, =0x00110002
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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ldr r1, =0x00100328
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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mov r2, #0x100000
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6: subs r2, r2, #1
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bne 6b
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ldr r1, =0x0a100000
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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mov r2, #0x100000
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7: subs r2, r2, #1
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bne 7b
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ldr r1, =0xe000008e
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str r1, [r0, #0x1C] @DMC_PHYCONTROL1
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ldr r1, =0xe0000086
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str r1, [r0, #0x1C] @DMC_PHYCONTROL1
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mov r2, #0x100000
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8: subs r2, r2, #1
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bne 8b
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/* DREX1 */
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ldr r0, =EXYNOS4_DMC1_BASE @0x10410000
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ldr r1, =0xe0000086
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str r1, [r0, #0x1C] @DMC_PHYCONTROL1
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ldr r1, =0xE3855703
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str r1, [r0, #0x44] @DMC_PHYZQCONTROL
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mov r2, #0x100000
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1: subs r2, r2, #1
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bne 1b
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ldr r1, =0xe000008e
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str r1, [r0, #0x1C] @DMC_PHYCONTROL1
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ldr r1, =0xe0000086
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str r1, [r0, #0x1C] @DMC_PHYCONTROL1
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ldr r1, =0x71101008
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str r1, [r0, #0x18] @DMC_PHYCONTROL0
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ldr r1, =0x7110100A
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str r1, [r0, #0x18] @DMC_PHYCONTROL0
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ldr r1, =0xe0000086
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str r1, [r0, #0x1C] @DMC_PHYCONTROL1
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ldr r1, =0x7110100B
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str r1, [r0, #0x18] @DMC_PHYCONTROL0
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ldr r1, =0x00000000
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str r1, [r0, #0x20] @DMC_PHYCONTROL2
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ldr r1, =0x0FFF301a
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str r1, [r0, #0x00] @DMC_CONCONTROL
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ldr r1, =0x00312640
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str r1, [r0, #0x04] @DMC_MEMCONTROL]
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#ifdef CONFIG_MIU_LINEAR
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ldr r1, =0x40e01323
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str r1, [r0, #0x08] @DMC_MEMCONFIG0
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ldr r1, =0x60e01323
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str r1, [r0, #0x0C] @DMC_MEMCONFIG1
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#else /* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
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ldr r1, =0x20e01323
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str r1, [r0, #0x08] @DMC_MEMCONFIG0
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ldr r1, =0x40e01323
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str r1, [r0, #0x0C] @DMC_MEMCONFIG1
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#endif
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ldr r1, =0xff000000
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str r1, [r0, #0x14] @DMC_PRECHCONFIG
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ldr r1, =0x000000BC
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str r1, [r0, #0x30] @DMC_TIMINGAREF
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#ifdef DRAM_CLK_330
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ldr r1, =0x3545548d
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str r1, [r0, #0x34] @DMC_TIMINGROW
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ldr r1, =0x45430506
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str r1, [r0, #0x38] @DMC_TIMINGDATA
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ldr r1, =0x4439033c
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str r1, [r0, #0x3C] @DMC_TIMINGPOWER
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#endif
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#ifdef DRAM_CLK_400
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ldr r1, =0x4046654f
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str r1, [r0, #0x34] @DMC_TIMINGROW
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ldr r1, =0x56500506
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str r1, [r0, #0x38] @DMC_TIMINGDATA
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ldr r1, =0x5444033d
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str r1, [r0, #0x3C] @DMC_TIMINGPOWER
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#endif
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ldr r1, =0x07000000
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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mov r2, #0x100000
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2: subs r2, r2, #1
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bne 2b
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ldr r1, =0x00020000
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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ldr r1, =0x00030000
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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ldr r1, =0x00010002
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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ldr r1, =0x00000328
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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mov r2, #0x100000
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3: subs r2, r2, #1
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bne 3b
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ldr r1, =0x0a000000
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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mov r2, #0x100000
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4: subs r2, r2, #1
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bne 4b
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ldr r1, =0x07100000
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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mov r2, #0x100000
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5: subs r2, r2, #1
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bne 5b
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ldr r1, =0x00120000
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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ldr r1, =0x00130000
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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ldr r1, =0x00110002
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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ldr r1, =0x00100328
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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mov r2, #0x100000
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6: subs r2, r2, #1
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bne 6b
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ldr r1, =0x0a100000
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str r1, [r0, #0x10] @DMC_DIRECTCMD
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mov r2, #0x100000
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7: subs r2, r2, #1
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bne 7b
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ldr r1, =0xe000008e
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str r1, [r0, #0x1C] @DMC_PHYCONTROL1
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ldr r1, =0xe0000086
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str r1, [r0, #0x1C] @DMC_PHYCONTROL1
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mov r2, #0x100000
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8: subs r2, r2, #1
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bne 8b
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/* turn on DREX0, DREX1 */
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ldr r0, =0x10400000 @APB_DMC_0_BASE
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ldr r1, =0x0FFF303a
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str r1, [r0, #0x00] @DMC_CONCONTROL
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ldr r0, =0x10410000 @APB_DMC_1_BASE
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ldr r1, =0x0FFF303a
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str r1, [r0, #0x00] @DMC_CONCONTROL
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mov pc, lr
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