upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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84 lines
2.7 KiB
84 lines
2.7 KiB
/*
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* Copyright (C) 2009 Marc Kleine-Budde <mkl@pengutronix.de>
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*
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* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef __ASM_ARCH_MC9SDZ60_H
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#define __ASM_ARCH_MC9SDZ60_H
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/**
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* Register addresses for the MC9SDZ60
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*
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* @note: these match those in the kernel drivers/mxc/mcu_pmic/mc9s08dz60.h
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* but not include/linux/mfd/mc9s08dz60/pmic.h
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*
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*/
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enum mc9sdz60_reg {
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MC9SDZ60_REG_VERSION = 0x00,
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/* reserved 0x01 */
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MC9SDZ60_REG_SECS = 0x02,
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MC9SDZ60_REG_MINS = 0x03,
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MC9SDZ60_REG_HRS = 0x04,
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MC9SDZ60_REG_DAY = 0x05,
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MC9SDZ60_REG_DATE = 0x06,
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MC9SDZ60_REG_MONTH = 0x07,
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MC9SDZ60_REG_YEAR = 0x08,
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MC9SDZ60_REG_ALARM_SECS = 0x09,
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MC9SDZ60_REG_ALARM_MINS = 0x0a,
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MC9SDZ60_REG_ALARM_HRS = 0x0b,
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/* reserved 0x0c */
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/* reserved 0x0d */
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MC9SDZ60_REG_TS_CONTROL = 0x0e,
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MC9SDZ60_REG_X_LOW = 0x0f,
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MC9SDZ60_REG_Y_LOW = 0x10,
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MC9SDZ60_REG_XY_HIGH = 0x11,
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MC9SDZ60_REG_X_LEFT_LOW = 0x12,
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MC9SDZ60_REG_X_LEFT_HIGH = 0x13,
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MC9SDZ60_REG_X_RIGHT = 0x14,
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MC9SDZ60_REG_Y_TOP_LOW = 0x15,
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MC9SDZ60_REG_Y_TOP_HIGH = 0x16,
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MC9SDZ60_REG_Y_BOTTOM = 0x17,
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/* reserved 0x18 */
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/* reserved 0x19 */
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MC9SDZ60_REG_RESET_1 = 0x1a,
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MC9SDZ60_REG_RESET_2 = 0x1b,
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MC9SDZ60_REG_POWER_CTL = 0x1c,
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MC9SDZ60_REG_DELAY_CONFIG = 0x1d,
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/* reserved 0x1e */
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/* reserved 0x1f */
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MC9SDZ60_REG_GPIO_1 = 0x20,
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MC9SDZ60_REG_GPIO_2 = 0x21,
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MC9SDZ60_REG_KPD_1 = 0x22,
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MC9SDZ60_REG_KPD_2 = 0x23,
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MC9SDZ60_REG_KPD_CONTROL = 0x24,
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MC9SDZ60_REG_INT_ENABLE_1 = 0x25,
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MC9SDZ60_REG_INT_ENABLE_2 = 0x26,
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MC9SDZ60_REG_INT_FLAG_1 = 0x27,
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MC9SDZ60_REG_INT_FLAG_2 = 0x28,
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MC9SDZ60_REG_DES_FLAG = 0x29,
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};
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extern u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg);
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extern void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val);
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#endif /* __ASM_ARCH_MC9SDZ60_H */
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