upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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228 lines
7.4 KiB
228 lines
7.4 KiB
/*
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* Based on Modifications by Alan Lu / Artila and
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* Rick Bronson <rick@efn.org>
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*
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* Configuration settings for the Artila M-501 starter kit,
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* with V02 processor card.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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/* from 18.432 MHz crystal (18432000 / 4 * 39) */
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#define AT91C_MAIN_CLOCK 179712000
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/* Perip clock (AT91C_MASTER_CLOCK / 3) */
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#define AT91C_MASTER_CLOCK 59904000
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#define AT91_SLOW_CLOCK 32768 /* slow clock */
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#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
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#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_MENUPROMPT "."
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/*
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* LowLevel Init
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*/
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#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
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/* flash */
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#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
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#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
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/* clocks */
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#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
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#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
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/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
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#define CONFIG_SYS_MCKR_VAL 0x00000202
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/* sdram */
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#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
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#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
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#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
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#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
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#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
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#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
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#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
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#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
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#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
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#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
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#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
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#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
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#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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#define CONFIG_BAUDRATE 115200
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/* Hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
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#define CONFIG_SYS_AT91C_BRGR_DIVISOR 33
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/*
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* Hardware drivers
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*/
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_FLASH_PROTECTION /*for Intel P30 Flash*/
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#define CONFIG_HARD_I2C
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#define CONFIG_SYS_I2C_SPEED 100
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#define CONFIG_SYS_I2C_SLAVE 0
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#define CONFIG_SYS_CONSOLE_INFO_QUIET
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#undef CONFIG_ENV_IS_IN_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_AT24C16
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#define CONFIG_SYS_I2C_RTC_ADDR 0x32
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#undef CONFIG_RTC_DS1338
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#define CONFIG_RTC_RS5C372A
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#undef CONFIG_POST
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#define CONFIG_M501SK
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#define CONFIG_CMC_PU2
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/* define one of these to choose the DBGU, USART0 or USART1 as console */
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#define CONFIG_AT91RM9200_USART
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#define CONFIG_DBGU
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#undef CONFIG_USART0
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#undef CONFIG_USART1
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#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
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#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
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#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200 " \
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"initrd=0x20800000,8192000 ramdisk_size=15360 " \
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"root=/dev/ram0 rw mtdparts=phys_mapped_flash:" \
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"128k(loader)ro,128k(reserved)ro,1408k(linux)" \
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"ro,2560k(ramdisk)ro,-(userdisk)"
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#define CONFIG_BOOTCOMMAND "bootm 10040000 101a0000"
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#define CONFIG_BOOTDELAY 1
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_IPADDR 192.168.1.100
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#define CONFIG_SERVERIP 192.168.1.1
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#define CONFIG_GATEWAYIP 192.168.1.254
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_BOOTFILE uImage
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#define CONFIG_ETHADDR 00:13:48:aa:bb:cc
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#define CONFIG_ENV_OVERWRITE 1
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#define BOARD_LATE_INIT
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"unlock=yes\0"
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#define CONFIG_CMD_JFFS2
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#undef CONFIG_CMD_EEPROM
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_RUN
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_POST
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#define CONFIG_CMD_MISC
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#define CONFIG_CMD_LOADS
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#define CONFIG_CMD_IMI
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_PROMPT_HUSH_PS2 ">>"
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#define CONFIG_SYS_MAX_NAND_DEVICE 0 /* Max number of NAND devices */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x20000000
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#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
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#define CONFIG_SYS_MEMTEST_START 0x21000000 /* PHYS_SDRAM */
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/* CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 */
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#define CONFIG_SYS_MEMTEST_END 0x00100000
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#define CONFIG_NET_MULTI 1
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#ifdef CONFIG_NET_MULTI
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#define CONFIG_DRIVER_AT91EMAC 1
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#define CONFIG_SYS_RX_ETH_BUFFER 8
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#else
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#define CONFIG_DRIVER_ETHER 1
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#endif
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_AT91C_USE_RMII
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#define PHYS_FLASH_1 0x10000000
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#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
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#ifdef CONFIG_ENV_IS_IN_DATAFLASH
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#define CONFIG_ENV_OFFSET 0x20000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
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#define CONFIG_ENV_SIZE 0x2000
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#else
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x00020000)
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#define CONFIG_ENV_SIZE 2048
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#endif
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#ifdef CONFIG_ENV_IS_IN_EEPROM
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#define CONFIG_ENV_OFFSET 1024
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#define CONFIG_ENV_SIZE 1024
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#endif
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#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
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/* use for protect flash sectors */
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#define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */
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#define CONFIG_SYS_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
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#define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200 , 19200, 38400, 57600, 9600 }
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#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2
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#define CONFIG_STACKSIZE (32*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#error CONFIG_USE_IRQ not supported
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#endif
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#endif
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