upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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186 lines
5.8 KiB
186 lines
5.8 KiB
/*
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* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
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* Based on Atheros LSDK/QSDK
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <mach/ar71xx_regs.h>
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#define MK_PLL_CONF(divint, refdiv, range, outdiv) \
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(((0x3F & divint) << 10) | \
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((0x1F & refdiv) << 16) | \
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((0x1 & range) << 21) | \
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((0x7 & outdiv) << 23) )
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#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
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(((0x3 & (cpudiv - 1)) << 5) | \
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((0x3 & (ddrdiv - 1)) << 10) | \
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((0x3 & (ahbdiv - 1)) << 15) )
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#define SET_FIELD(name, v) (((v) & QCA953X_##name##_MASK) << \
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QCA953X_##name##_SHIFT)
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#define DPLL2_KI(v) SET_FIELD(SRIF_DPLL2_KI, v)
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#define DPLL2_KD(v) SET_FIELD(SRIF_DPLL2_KD, v)
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#define DPLL2_PWD QCA953X_SRIF_DPLL2_PWD
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#define MK_DPLL2(ki, kd) (DPLL2_KI(ki) | DPLL2_KD(kd) | DPLL2_PWD)
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#define PLL_CPU_NFRAC(v) SET_FIELD(PLL_CPU_CONFIG_NFRAC, v)
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#define PLL_CPU_NINT(v) SET_FIELD(PLL_CPU_CONFIG_NINT, v)
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#define PLL_CPU_REFDIV(v) SET_FIELD(PLL_CPU_CONFIG_REFDIV, v)
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#define PLL_CPU_OUTDIV(v) SET_FIELD(PLL_CPU_CONFIG_OUTDIV, v)
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#define MK_PLL_CPU_CONF(frac, nint, ref, outdiv) \
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(PLL_CPU_NFRAC(frac) | \
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PLL_CPU_NINT(nint) | \
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PLL_CPU_REFDIV(ref) | \
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PLL_CPU_OUTDIV(outdiv))
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#define PLL_DDR_NFRAC(v) SET_FIELD(PLL_DDR_CONFIG_NFRAC, v)
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#define PLL_DDR_NINT(v) SET_FIELD(PLL_DDR_CONFIG_NINT, v)
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#define PLL_DDR_REFDIV(v) SET_FIELD(PLL_DDR_CONFIG_REFDIV, v)
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#define PLL_DDR_OUTDIV(v) SET_FIELD(PLL_DDR_CONFIG_OUTDIV, v)
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#define MK_PLL_DDR_CONF(frac, nint, ref, outdiv) \
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(PLL_DDR_NFRAC(frac) | \
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PLL_DDR_REFDIV(ref) | \
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PLL_DDR_NINT(nint) | \
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PLL_DDR_OUTDIV(outdiv) | \
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QCA953X_PLL_CONFIG_PWD)
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#define PLL_CPU_CONF_VAL MK_PLL_CPU_CONF(0, 26, 1, 0)
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#define PLL_DDR_CONF_VAL MK_PLL_DDR_CONF(0, 15, 1, 0)
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#define PLL_CLK_CTRL_PLL_BYPASS (QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS | \
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QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS | \
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QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
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#define PLL_CLK_CTRL_CPU_DIV(v) SET_FIELD(PLL_CLK_CTRL_CPU_POST_DIV, v)
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#define PLL_CLK_CTRL_DDR_DIV(v) SET_FIELD(PLL_CLK_CTRL_DDR_POST_DIV, v)
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#define PLL_CLK_CTRL_AHB_DIV(v) SET_FIELD(PLL_CLK_CTRL_AHB_POST_DIV, v)
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#define MK_PLL_CLK_CTRL(cpu, ddr, ahb) \
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(PLL_CLK_CTRL_CPU_DIV(cpu) | \
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PLL_CLK_CTRL_DDR_DIV(ddr) | \
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PLL_CLK_CTRL_AHB_DIV(ahb))
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#define PLL_CLK_CTRL_VAL (MK_PLL_CLK_CTRL(0, 0, 2) | \
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PLL_CLK_CTRL_PLL_BYPASS | \
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QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL | \
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QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
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#define PLL_DDR_DIT_FRAC_MAX(v) SET_FIELD(PLL_DDR_DIT_FRAC_MAX, v)
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#define PLL_DDR_DIT_FRAC_MIN(v) SET_FIELD(PLL_DDR_DIT_FRAC_MIN, v)
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#define PLL_DDR_DIT_FRAC_STEP(v) SET_FIELD(PLL_DDR_DIT_FRAC_STEP, v)
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#define PLL_DDR_DIT_UPD_CNT(v) SET_FIELD(PLL_DDR_DIT_UPD_CNT, v)
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#define PLL_CPU_DIT_FRAC_MAX(v) SET_FIELD(PLL_CPU_DIT_FRAC_MAX, v)
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#define PLL_CPU_DIT_FRAC_MIN(v) SET_FIELD(PLL_CPU_DIT_FRAC_MIN, v)
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#define PLL_CPU_DIT_FRAC_STEP(v) SET_FIELD(PLL_CPU_DIT_FRAC_STEP, v)
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#define PLL_CPU_DIT_UPD_CNT(v) SET_FIELD(PLL_CPU_DIT_UPD_CNT, v)
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#define MK_PLL_DDR_DIT_FRAC(max, min, step, cnt) \
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(QCA953X_PLL_DIT_FRAC_EN | \
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PLL_DDR_DIT_FRAC_MAX(max) | \
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PLL_DDR_DIT_FRAC_MIN(min) | \
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PLL_DDR_DIT_FRAC_STEP(step) | \
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PLL_DDR_DIT_UPD_CNT(cnt))
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#define MK_PLL_CPU_DIT_FRAC(max, min, step, cnt) \
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(QCA953X_PLL_DIT_FRAC_EN | \
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PLL_CPU_DIT_FRAC_MAX(max) | \
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PLL_CPU_DIT_FRAC_MIN(min) | \
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PLL_CPU_DIT_FRAC_STEP(step) | \
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PLL_CPU_DIT_UPD_CNT(cnt))
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#define PLL_CPU_DIT_FRAC_VAL MK_PLL_CPU_DIT_FRAC(63, 0, 1, 15)
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#define PLL_DDR_DIT_FRAC_VAL MK_PLL_DDR_DIT_FRAC(763, 635, 1, 15)
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.text
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.set noreorder
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LEAF(lowlevel_init)
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/* RTC Reset */
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li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
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lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
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li t2, 0x08000000
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or t1, t1, t2
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sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
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nop
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lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
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li t2, 0xf7ffffff
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and t1, t1, t2
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sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
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nop
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/* RTC Force Wake */
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li t0, CKSEG1ADDR(QCA953X_RTC_BASE)
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li t1, 0x01
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sw t1, QCA953X_RTC_REG_SYNC_RESET(t0)
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nop
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nop
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/* Wait for RTC in on state */
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1:
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lw t1, QCA953X_RTC_REG_SYNC_STATUS(t0)
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andi t1, t1, 0x02
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beqz t1, 1b
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nop
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li t0, CKSEG1ADDR(QCA953X_SRIF_BASE)
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li t1, MK_DPLL2(2, 16)
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sw t1, QCA953X_SRIF_BB_DPLL2_REG(t0)
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sw t1, QCA953X_SRIF_PCIE_DPLL2_REG(t0)
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sw t1, QCA953X_SRIF_DDR_DPLL2_REG(t0)
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sw t1, QCA953X_SRIF_CPU_DPLL2_REG(t0)
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li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
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lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
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ori t1, PLL_CLK_CTRL_PLL_BYPASS
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sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
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nop
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li t1, PLL_CPU_CONF_VAL
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sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
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nop
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li t1, PLL_DDR_CONF_VAL
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sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
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nop
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li t1, PLL_CLK_CTRL_VAL
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sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
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nop
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lw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
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li t2, ~QCA953X_PLL_CONFIG_PWD
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and t1, t1, t2
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sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
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nop
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lw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
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li t2, ~QCA953X_PLL_CONFIG_PWD
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and t1, t1, t2
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sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
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nop
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lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
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li t2, ~PLL_CLK_CTRL_PLL_BYPASS
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and t1, t1, t2
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sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
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nop
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li t1, PLL_DDR_DIT_FRAC_VAL
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sw t1, QCA953X_PLL_DDR_DIT_FRAC_REG(t0)
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nop
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li t1, PLL_CPU_DIT_FRAC_VAL
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sw t1, QCA953X_PLL_CPU_DIT_FRAC_REG(t0)
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nop
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li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
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lui t1, 0x03fc
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sw t1, 0xb4(t0)
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nop
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jr ra
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nop
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END(lowlevel_init)
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