upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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136 lines
3.2 KiB
136 lines
3.2 KiB
/*
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* (C) Copyright 2009
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* Matthias Fuchs, esd gmbh, matthias.fuchs@esd.eu
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*
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* (C) Copyright 2006
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* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
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* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
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* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
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* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
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* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
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*
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* (C) Copyright 2006-2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* define DEBUG for debug output */
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#undef DEBUG
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/ppc440.h>
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extern int denali_wait_for_dlllock(void);
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extern void denali_core_search_data_eye(void);
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struct sdram_conf_s {
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ulong size;
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int rows;
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int banks;
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};
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struct sdram_conf_s sdram_conf[] = {
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{(1024 << 20), 14, 8}, /* 1GByte: 4x2GBit, 14x10, 8 banks */
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{(512 << 20), 13, 8}, /* 512MByte: 4x1GBit, 13x10, 8 banks */
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{(256 << 20), 13, 4}, /* 256MByte: 4x512MBit, 13x10, 4 banks */
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};
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/*
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* initdram -- 440EPx's DDR controller is a DENALI Core
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*/
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int initdram_by_rb(int rows, int banks)
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{
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ulong speed = get_bus_freq(0);
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mtsdram(DDR0_02, 0x00000000);
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mtsdram(DDR0_00, 0x0000190A);
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mtsdram(DDR0_01, 0x01000000);
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mtsdram(DDR0_03, 0x02030602);
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mtsdram(DDR0_04, 0x0A020200);
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mtsdram(DDR0_05, 0x02020308);
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mtsdram(DDR0_06, 0x0102C812);
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mtsdram(DDR0_07, 0x000D0100);
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mtsdram(DDR0_08, 0x02430001);
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mtsdram(DDR0_09, 0x00011D5F);
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mtsdram(DDR0_10, 0x00000100);
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mtsdram(DDR0_11, 0x0027C800);
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mtsdram(DDR0_12, 0x00000003);
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mtsdram(DDR0_14, 0x00000000);
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mtsdram(DDR0_17, 0x19000000);
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mtsdram(DDR0_18, 0x19191919);
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mtsdram(DDR0_19, 0x19191919);
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mtsdram(DDR0_20, 0x0B0B0B0B);
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mtsdram(DDR0_21, 0x0B0B0B0B);
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mtsdram(DDR0_22, 0x00267F0B);
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mtsdram(DDR0_23, 0x00000000);
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mtsdram(DDR0_24, 0x01010002);
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if (speed > 133333334)
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mtsdram(DDR0_26, 0x5B26050C);
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else
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mtsdram(DDR0_26, 0x5B260408);
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mtsdram(DDR0_27, 0x0000682B);
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mtsdram(DDR0_28, 0x00000000);
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mtsdram(DDR0_31, 0x00000000);
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mtsdram(DDR0_42,
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DDR0_42_ADDR_PINS_DECODE(14 - rows) |
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0x00000006);
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mtsdram(DDR0_43,
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DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) |
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0x030A0200);
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mtsdram(DDR0_44, 0x00000003);
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mtsdram(DDR0_02, 0x00000001);
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denali_wait_for_dlllock();
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#ifdef CONFIG_DDR_DATA_EYE
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/*
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* Perform data eye search if requested.
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*/
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denali_core_search_data_eye();
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#endif
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/*
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* Clear possible errors resulting from data-eye-search.
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* If not done, then we could get an interrupt later on when
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* exceptions are enabled.
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*/
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set_mcsr(get_mcsr());
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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phys_size_t size;
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int n;
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/* go through supported memory configurations */
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for (n = 0; n < ARRAY_SIZE(sdram_conf); n++) {
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size = sdram_conf[n].size;
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/* program TLB entries */
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program_tlb(0, CONFIG_SYS_SDRAM_BASE, size,
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TLB_WORD2_I_ENABLE);
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/*
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* setup denali core
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*/
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initdram_by_rb(sdram_conf[n].rows,
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sdram_conf[n].banks);
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/* check for suitable configuration */
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if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size)
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return size;
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/* delete TLB entries */
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remove_tlb(CONFIG_SYS_SDRAM_BASE, size);
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}
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return 0;
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}
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