upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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255 lines
7.0 KiB
255 lines
7.0 KiB
/*
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* (C) Copyright 2010 Samsung Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef __ASM_ARM_ARCH_CLOCK_H_
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#define __ASM_ARM_ARCH_CLOCK_H_
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#ifndef __ASSEMBLY__
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struct exynos4_clock {
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unsigned char res1[0x4200];
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unsigned int src_leftbus;
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unsigned char res2[0x1fc];
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unsigned int mux_stat_leftbus;
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unsigned char res4[0xfc];
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unsigned int div_leftbus;
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unsigned char res5[0xfc];
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unsigned int div_stat_leftbus;
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unsigned char res6[0x1fc];
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unsigned int gate_ip_leftbus;
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unsigned char res7[0x1fc];
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unsigned int clkout_leftbus;
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unsigned int clkout_leftbus_div_stat;
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unsigned char res8[0x37f8];
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unsigned int src_rightbus;
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unsigned char res9[0x1fc];
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unsigned int mux_stat_rightbus;
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unsigned char res10[0xfc];
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unsigned int div_rightbus;
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unsigned char res11[0xfc];
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unsigned int div_stat_rightbus;
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unsigned char res12[0x1fc];
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unsigned int gate_ip_rightbus;
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unsigned char res13[0x1fc];
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unsigned int clkout_rightbus;
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unsigned int clkout_rightbus_div_stat;
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unsigned char res14[0x3608];
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unsigned int epll_lock;
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unsigned char res15[0xc];
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unsigned int vpll_lock;
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unsigned char res16[0xec];
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unsigned int epll_con0;
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unsigned int epll_con1;
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unsigned char res17[0x8];
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unsigned int vpll_con0;
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unsigned int vpll_con1;
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unsigned char res18[0xe8];
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unsigned int src_top0;
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unsigned int src_top1;
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unsigned char res19[0x8];
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unsigned int src_cam;
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unsigned int src_tv;
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unsigned int src_mfc;
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unsigned int src_g3d;
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unsigned int src_image;
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unsigned int src_lcd0;
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unsigned int src_lcd1;
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unsigned int src_maudio;
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unsigned int src_fsys;
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unsigned char res20[0xc];
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unsigned int src_peril0;
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unsigned int src_peril1;
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unsigned char res21[0xb8];
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unsigned int src_mask_top;
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unsigned char res22[0xc];
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unsigned int src_mask_cam;
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unsigned int src_mask_tv;
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unsigned char res23[0xc];
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unsigned int src_mask_lcd0;
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unsigned int src_mask_lcd1;
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unsigned int src_mask_maudio;
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unsigned int src_mask_fsys;
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unsigned char res24[0xc];
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unsigned int src_mask_peril0;
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unsigned int src_mask_peril1;
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unsigned char res25[0xb8];
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unsigned int mux_stat_top;
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unsigned char res26[0x14];
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unsigned int mux_stat_mfc;
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unsigned int mux_stat_g3d;
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unsigned int mux_stat_image;
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unsigned char res27[0xdc];
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unsigned int div_top;
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unsigned char res28[0xc];
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unsigned int div_cam;
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unsigned int div_tv;
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unsigned int div_mfc;
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unsigned int div_g3d;
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unsigned int div_image;
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unsigned int div_lcd0;
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unsigned int div_lcd1;
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unsigned int div_maudio;
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unsigned int div_fsys0;
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unsigned int div_fsys1;
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unsigned int div_fsys2;
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unsigned int div_fsys3;
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unsigned int div_peril0;
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unsigned int div_peril1;
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unsigned int div_peril2;
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unsigned int div_peril3;
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unsigned int div_peril4;
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unsigned int div_peril5;
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unsigned char res29[0x18];
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unsigned int div2_ratio;
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unsigned char res30[0x8c];
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unsigned int div_stat_top;
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unsigned char res31[0xc];
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unsigned int div_stat_cam;
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unsigned int div_stat_tv;
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unsigned int div_stat_mfc;
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unsigned int div_stat_g3d;
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unsigned int div_stat_image;
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unsigned int div_stat_lcd0;
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unsigned int div_stat_lcd1;
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unsigned int div_stat_maudio;
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unsigned int div_stat_fsys0;
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unsigned int div_stat_fsys1;
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unsigned int div_stat_fsys2;
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unsigned int div_stat_fsys3;
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unsigned int div_stat_peril0;
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unsigned int div_stat_peril1;
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unsigned int div_stat_peril2;
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unsigned int div_stat_peril3;
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unsigned int div_stat_peril4;
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unsigned int div_stat_peril5;
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unsigned char res32[0x18];
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unsigned int div2_stat;
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unsigned char res33[0x29c];
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unsigned int gate_ip_cam;
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unsigned int gate_ip_tv;
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unsigned int gate_ip_mfc;
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unsigned int gate_ip_g3d;
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unsigned int gate_ip_image;
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unsigned int gate_ip_lcd0;
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unsigned int gate_ip_lcd1;
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unsigned char res34[0x4];
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unsigned int gate_ip_fsys;
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unsigned char res35[0x8];
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unsigned int gate_ip_gps;
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unsigned int gate_ip_peril;
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unsigned char res36[0xc];
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unsigned int gate_ip_perir;
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unsigned char res37[0xc];
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unsigned int gate_block;
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unsigned char res38[0x8c];
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unsigned int clkout_cmu_top;
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unsigned int clkout_cmu_top_div_stat;
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unsigned char res39[0x37f8];
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unsigned int src_dmc;
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unsigned char res40[0xfc];
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unsigned int src_mask_dmc;
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unsigned char res41[0xfc];
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unsigned int mux_stat_dmc;
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unsigned char res42[0xfc];
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unsigned int div_dmc0;
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unsigned int div_dmc1;
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unsigned char res43[0xf8];
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unsigned int div_stat_dmc0;
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unsigned int div_stat_dmc1;
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unsigned char res44[0x2f8];
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unsigned int gate_ip_dmc;
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unsigned char res45[0xfc];
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unsigned int clkout_cmu_dmc;
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unsigned int clkout_cmu_dmc_div_stat;
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unsigned char res46[0x5f8];
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unsigned int dcgidx_map0;
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unsigned int dcgidx_map1;
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unsigned int dcgidx_map2;
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unsigned char res47[0x14];
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unsigned int dcgperf_map0;
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unsigned int dcgperf_map1;
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unsigned char res48[0x18];
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unsigned int dvcidx_map;
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unsigned char res49[0x1c];
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unsigned int freq_cpu;
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unsigned int freq_dpm;
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unsigned char res50[0x18];
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unsigned int dvsemclk_en;
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unsigned int maxperf;
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unsigned char res51[0x2f78];
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unsigned int apll_lock;
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unsigned char res52[0x4];
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unsigned int mpll_lock;
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unsigned char res53[0xf4];
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unsigned int apll_con0;
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unsigned int apll_con1;
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unsigned int mpll_con0;
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unsigned int mpll_con1;
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unsigned char res54[0xf0];
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unsigned int src_cpu;
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unsigned char res55[0x1fc];
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unsigned int mux_stat_cpu;
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unsigned char res56[0xfc];
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unsigned int div_cpu0;
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unsigned int div_cpu1;
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unsigned char res57[0xf8];
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unsigned int div_stat_cpu0;
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unsigned int div_stat_cpu1;
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unsigned char res58[0x3f8];
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unsigned int clkout_cmu_cpu;
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unsigned int clkout_cmu_cpu_div_stat;
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unsigned char res59[0x5f8];
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unsigned int armclk_stopctrl;
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unsigned int atclk_stopctrl;
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unsigned char res60[0x8];
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unsigned int parityfail_status;
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unsigned int parityfail_clear;
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unsigned char res61[0xe8];
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unsigned int apll_con0_l8;
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unsigned int apll_con0_l7;
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unsigned int apll_con0_l6;
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unsigned int apll_con0_l5;
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unsigned int apll_con0_l4;
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unsigned int apll_con0_l3;
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unsigned int apll_con0_l2;
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unsigned int apll_con0_l1;
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unsigned int iem_control;
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unsigned char res62[0xdc];
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unsigned int apll_con1_l8;
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unsigned int apll_con1_l7;
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unsigned int apll_con1_l6;
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unsigned int apll_con1_l5;
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unsigned int apll_con1_l4;
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unsigned int apll_con1_l3;
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unsigned int apll_con1_l2;
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unsigned int apll_con1_l1;
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unsigned char res63[0xe0];
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unsigned int div_iem_l8;
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unsigned int div_iem_l7;
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unsigned int div_iem_l6;
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unsigned int div_iem_l5;
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unsigned int div_iem_l4;
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unsigned int div_iem_l3;
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unsigned int div_iem_l2;
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unsigned int div_iem_l1;
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};
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#endif
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#endif
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