upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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68 lines
1.6 KiB
68 lines
1.6 KiB
/*
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* (C) Copyright 2001
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/ppc4xx.h>
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#include <asm/processor.h>
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/*
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* include common flash code (for esd boards)
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*/
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#include "../common/flash.c"
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size (vu_long *addr, flash_info_t *info);
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static void flash_get_offsets (ulong base, flash_info_t *info);
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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unsigned long size_b0;
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int i;
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uint pbcr;
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unsigned long base_b0;
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/* Init: no FLASHes known */
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for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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}
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/* Static FLASH Bank configuration here - FIXME XXX */
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size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
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if (flash_info[0].flash_id == FLASH_UNKNOWN) {
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
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size_b0, size_b0<<20);
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}
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/* Setup offsets */
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flash_get_offsets (-size_b0, &flash_info[0]);
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/* Re-do sizing to get full correct info */
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mtdcr(EBC0_CFGADDR, PB0CR);
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pbcr = mfdcr(EBC0_CFGDATA);
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mtdcr(EBC0_CFGADDR, PB0CR);
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base_b0 = -size_b0;
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pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
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mtdcr(EBC0_CFGDATA, pbcr);
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/* printf("PB1CR = %x\n", pbcr); */
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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-monitor_flash_len,
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0xffffffff,
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&flash_info[0]);
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flash_info[0].size = size_b0;
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return (size_b0);
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}
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