upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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274 lines
6.6 KiB
274 lines
6.6 KiB
/*
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* Board functions for Siemens CORVUS (AT91SAM9G45) based board
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* (C) Copyright 2013 Siemens AG
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*
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* Based on:
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* U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/at91sam9g45_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/clk.h>
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#include <lcd.h>
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#include <atmel_lcdc.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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#include <net.h>
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#endif
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#include <netdev.h>
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#include <spi.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void corvus_nand_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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unsigned long csa;
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/* Enable CS3 */
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csa = readl(&matrix->ebicsa);
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csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
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writel(csa, &matrix->ebicsa);
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/* Configure SMC CS3 for NAND/SmartMedia */
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writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
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AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_MODE_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_MODE_DBW_8 |
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#endif
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AT91_SMC_MODE_TDF_CYCLE(3),
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&smc->cs[3].mode);
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at91_periph_clk_enable(ATMEL_ID_PIOC);
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at91_periph_clk_enable(ATMEL_ID_PIOA);
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/* Enable NandFlash */
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at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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}
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#if defined(CONFIG_SPL_BUILD)
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#include <spl.h>
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#include <nand.h>
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void at91_spl_board_init(void)
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{
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/*
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* For on the sam9m10g45ek board, the chip wm9711 stay in the test
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* mode, so it need do some action to exit mode.
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*/
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at91_set_gpio_output(AT91_PIN_PD7, 0);
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at91_set_gpio_output(AT91_PIN_PD8, 0);
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at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
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at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
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at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
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at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
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at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
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corvus_nand_hw_init();
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/* Configure recovery button PINs */
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at91_set_gpio_input(AT91_PIN_PB7, 1);
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/* check if button is pressed */
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if (at91_get_gpio_value(AT91_PIN_PB7) == 0) {
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u32 boot_device;
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debug("Recovery button pressed\n");
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boot_device = spl_boot_device();
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switch (boot_device) {
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#ifdef CONFIG_SPL_NAND_SUPPORT
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case BOOT_DEVICE_NAND:
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nand_init();
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spl_nand_erase_one(0, 0);
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break;
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#endif
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}
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}
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}
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#include <asm/arch/atmel_mpddrc.h>
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static void ddr2_conf(struct atmel_mpddr *ddr2)
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{
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ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
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ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
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ATMEL_MPDDRC_CR_NR_ROW_14 |
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ATMEL_MPDDRC_CR_DIC_DS |
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ATMEL_MPDDRC_CR_DQMS_SHARED |
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ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
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ddr2->rtr = 0x24b;
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ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
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2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
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2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
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8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */
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2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
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1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
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1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
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2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
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ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
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200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
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16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
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14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
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ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
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0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
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7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
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2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
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}
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void mem_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct atmel_mpddr ddr2;
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ddr2_conf(&ddr2);
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/* enable DDR2 clock */
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writel(AT91_PMC_DDR, &pmc->scer);
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
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}
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#endif
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#ifdef CONFIG_CMD_USB
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static void taurus_usb_hw_init(void)
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{
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at91_periph_clk_enable(ATMEL_ID_PIODE);
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at91_set_gpio_output(AT91_PIN_PD1, 0);
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at91_set_gpio_output(AT91_PIN_PD3, 0);
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}
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#endif
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#ifdef CONFIG_MACB
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static void corvus_macb_hw_init(void)
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{
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/* Enable clock */
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at91_periph_clk_enable(ATMEL_ID_EMAC);
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/*
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* Disable pull-up on:
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* RXDV (PA15) => PHY normal mode (not Test mode)
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* ERX0 (PA12) => PHY ADDR0
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* ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
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*
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* PHY has internal pull-down
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*/
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at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
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at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
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at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
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at91_phy_reset();
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/* Re-enable pull-up */
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at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
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at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
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at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
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/* And the pins. */
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at91_macb_hw_init();
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}
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#endif
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int board_early_init_f(void)
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{
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at91_seriald_hw_init();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_CMD_NAND
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corvus_nand_hw_init();
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#endif
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#ifdef CONFIG_ATMEL_SPI
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at91_spi0_hw_init(1 << 4);
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#endif
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#ifdef CONFIG_HAS_DATAFLASH
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at91_spi0_hw_init(1 << 0);
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#endif
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#ifdef CONFIG_MACB
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corvus_macb_hw_init();
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#endif
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#ifdef CONFIG_CMD_USB
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taurus_usb_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
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#endif
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return rc;
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}
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/* SPI chip select control */
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && cs < 2;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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switch (slave->cs) {
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case 1:
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at91_set_gpio_output(AT91_PIN_PB18, 0);
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break;
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case 0:
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default:
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at91_set_gpio_output(AT91_PIN_PB3, 0);
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break;
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}
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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switch (slave->cs) {
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case 1:
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at91_set_gpio_output(AT91_PIN_PB18, 1);
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break;
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case 0:
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default:
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at91_set_gpio_output(AT91_PIN_PB3, 1);
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break;
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}
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}
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