upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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59 lines
1.6 KiB
59 lines
1.6 KiB
/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <pci.h>
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#include <smsc_sio1007.h>
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#include <asm/ibmpc.h>
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#include <asm/lpc_common.h>
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#include <asm/pci.h>
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#include <asm/arch/pch.h>
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#define SIO1007_RUNTIME_IOPORT 0x180
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int board_early_init_f(void)
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{
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struct udevice *pch;
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int ret;
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ret = uclass_first_device(UCLASS_PCH, &pch);
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if (ret)
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return ret;
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if (!pch)
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return -ENODEV;
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/* Initialize LPC interface to turn on superio chipset decode range */
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dm_pci_write_config16(pch, LPC_IO_DEC, COMA_DEC_RANGE | COMB_DEC_RANGE);
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dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | COMA_LPC_EN);
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dm_pci_write_config32(pch, LPC_GEN1_DEC, GEN_DEC_RANGE_256B |
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(SIO1007_IOPORT3 & 0xff00) | GEN_DEC_RANGE_EN);
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dm_pci_write_config32(pch, LPC_GEN2_DEC, GEN_DEC_RANGE_16B |
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SIO1007_RUNTIME_IOPORT | GEN_DEC_RANGE_EN);
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/* Enable legacy serial port at 0x3f8 */
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sio1007_enable_serial(SIO1007_IOPORT3, 0, UART0_BASE, UART0_IRQ);
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/* Enable SIO1007 runtime I/O port at 0x180 */
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sio1007_enable_runtime(SIO1007_IOPORT3, SIO1007_RUNTIME_IOPORT);
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/*
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* On Cougar Canyon 2 board, the RS232 transiver connected to serial
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* port 0 (0x3f8) is controlled by a GPIO pin (GPIO10) on the SIO1007.
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* Set the pin value to 1 to enable the RS232 transiver.
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*/
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sio1007_gpio_config(SIO1007_IOPORT3, 0, GPIO_DIR_OUTPUT,
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GPIO_POL_NO_INVERT, GPIO_TYPE_PUSH_PULL);
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sio1007_gpio_set_value(SIO1007_RUNTIME_IOPORT, 0, 1);
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return 0;
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}
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void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
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{
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return;
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}
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