upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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299 lines
7.5 KiB
299 lines
7.5 KiB
config ARCH_LS1012A
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bool
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select ARMV8_SET_SMPEN
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select FSL_LSCH2
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select SYS_FSL_DDR_BE
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select SYS_FSL_MMDC
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select SYS_FSL_ERRATUM_A010315
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select ARCH_EARLY_INIT_R
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select BOARD_EARLY_INIT_F
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config ARCH_LS1043A
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bool
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select ARMV8_SET_SMPEN
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select FSL_LSCH2
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select SYS_FSL_DDR
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select SYS_FSL_DDR_BE
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_ERRATUM_A008850
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select SYS_FSL_ERRATUM_A009660
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select SYS_FSL_ERRATUM_A009663
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select SYS_FSL_ERRATUM_A009929
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select SYS_FSL_ERRATUM_A009942
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select SYS_FSL_ERRATUM_A010315
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select SYS_FSL_ERRATUM_A010539
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_DDR4
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select ARCH_EARLY_INIT_R
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select BOARD_EARLY_INIT_F
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config ARCH_LS1046A
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bool
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select ARMV8_SET_SMPEN
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select FSL_LSCH2
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select SYS_FSL_DDR
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select SYS_FSL_DDR_BE
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_ERRATUM_A008336
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select SYS_FSL_ERRATUM_A008511
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select SYS_FSL_ERRATUM_A009801
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select SYS_FSL_ERRATUM_A009803
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select SYS_FSL_ERRATUM_A009942
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select SYS_FSL_ERRATUM_A010165
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select SYS_FSL_ERRATUM_A010539
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select SYS_FSL_HAS_DDR4
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select SYS_FSL_SRDS_2
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select ARCH_EARLY_INIT_R
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select BOARD_EARLY_INIT_F
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config ARCH_LS2080A
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bool
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select ARMV8_SET_SMPEN
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select ARM_ERRATA_826974
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select ARM_ERRATA_828024
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select ARM_ERRATA_829520
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select ARM_ERRATA_833471
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select FSL_LSCH3
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select SYS_FSL_DDR
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select SYS_FSL_DDR_LE
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_HAS_DP_DDR
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select SYS_FSL_HAS_SEC
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select SYS_FSL_HAS_DDR4
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select SYS_FSL_SEC_COMPAT_5
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select SYS_FSL_SEC_LE
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select SYS_FSL_SRDS_2
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select SYS_FSL_ERRATUM_A008336
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select SYS_FSL_ERRATUM_A008511
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select SYS_FSL_ERRATUM_A008514
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select SYS_FSL_ERRATUM_A008585
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select SYS_FSL_ERRATUM_A009635
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select SYS_FSL_ERRATUM_A009663
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select SYS_FSL_ERRATUM_A009801
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select SYS_FSL_ERRATUM_A009803
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select SYS_FSL_ERRATUM_A009942
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select SYS_FSL_ERRATUM_A010165
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select ARCH_EARLY_INIT_R
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select BOARD_EARLY_INIT_F
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config FSL_LSCH2
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bool
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_COMPAT_5
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select SYS_FSL_SEC_BE
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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config FSL_LSCH3
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bool
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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menu "Layerscape architecture"
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depends on FSL_LSCH2 || FSL_LSCH3
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config FSL_PCIE_COMPAT
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string "PCIe compatible of Kernel DT"
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depends on PCIE_LAYERSCAPE
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default "fsl,ls1012a-pcie" if ARCH_LS1012A
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default "fsl,ls1043a-pcie" if ARCH_LS1043A
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default "fsl,ls1046a-pcie" if ARCH_LS1046A
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default "fsl,ls2080a-pcie" if ARCH_LS2080A
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help
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This compatible is used to find pci controller node in Kernel DT
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to complete fixup.
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config HAS_FEATURE_GIC64K_ALIGN
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bool
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default y if ARCH_LS1043A
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config HAS_FEATURE_ENHANCED_MSI
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bool
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default y if ARCH_LS1043A
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menu "Layerscape PPA"
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config FSL_LS_PPA
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bool "FSL Layerscape PPA firmware support"
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depends on !ARMV8_PSCI
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select ARMV8_SEC_FIRMWARE_SUPPORT
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select SEC_FIRMWARE_ARMV8_PSCI
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select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
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help
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The FSL Primary Protected Application (PPA) is a software component
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which is loaded during boot stage, and then remains resident in RAM
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and runs in the TrustZone after boot.
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Say y to enable it.
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choice
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prompt "FSL Layerscape PPA firmware loading-media select"
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depends on FSL_LS_PPA
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default SYS_LS_PPA_FW_IN_XIP
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config SYS_LS_PPA_FW_IN_XIP
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bool "XIP"
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help
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Say Y here if the PPA firmware locate at XIP flash, such
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as NOR or QSPI flash.
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endchoice
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config SYS_LS_PPA_FW_ADDR
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hex "Address of PPA firmware loading from"
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depends on FSL_LS_PPA
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default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
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default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
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help
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If the PPA firmware locate at XIP flash, such as NOR or
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QSPI flash, this address is a directly memory-mapped.
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If it is in a serial accessed flash, such as NAND and SD
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card, it is a byte offset.
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endmenu
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config SYS_FSL_ERRATUM_A010315
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bool "Workaround for PCIe erratum A010315"
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config SYS_FSL_ERRATUM_A010539
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bool "Workaround for PIN MUX erratum A010539"
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config MAX_CPUS
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int "Maximum number of CPUs permitted for Layerscape"
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default 4 if ARCH_LS1043A
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default 4 if ARCH_LS1046A
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default 16 if ARCH_LS2080A
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default 1
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help
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Set this number to the maximum number of possible CPUs in the SoC.
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SoCs may have multiple clusters with each cluster may have multiple
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ports. If some ports are reserved but higher ports are used for
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cores, count the reserved ports. This will allocate enough memory
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in spin table to properly handle all cores.
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config SECURE_BOOT
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bool "Secure Boot"
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help
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Enable Freescale Secure Boot feature
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config QSPI_AHB_INIT
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bool "Init the QSPI AHB bus"
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help
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The default setting for QSPI AHB bus just support 3bytes addressing.
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But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
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bus for those flashes to support the full QSPI flash size.
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config SYS_FSL_IFC_BANK_COUNT
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int "Maximum banks of Integrated flash controller"
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depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
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default 4 if ARCH_LS1043A
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default 4 if ARCH_LS1046A
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default 8 if ARCH_LS2080A
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config SYS_FSL_HAS_DP_DDR
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bool
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config SYS_FSL_SRDS_1
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bool
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config SYS_FSL_SRDS_2
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bool
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config SYS_HAS_SERDES
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bool
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endmenu
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menu "Layerscape clock tree configuration"
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depends on FSL_LSCH2 || FSL_LSCH3
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config SYS_FSL_CLK
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bool "Enable clock tree initialization"
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default y
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config CLUSTER_CLK_FREQ
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int "Reference clock of core cluster"
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depends on ARCH_LS1012A
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default 100000000
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help
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This number is the reference clock frequency of core PLL.
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For most platforms, the core PLL and Platform PLL have the same
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reference clock, but for some platforms, LS1012A for instance,
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they are provided sepatately.
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config SYS_FSL_PCLK_DIV
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int "Platform clock divider"
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default 1 if ARCH_LS1043A
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default 1 if ARCH_LS1046A
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default 2
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help
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This is the divider that is used to derive Platform clock from
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Platform PLL, in another word:
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Platform_clk = Platform_PLL_freq / this_divider
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config SYS_FSL_DSPI_CLK_DIV
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int "DSPI clock divider"
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default 1 if ARCH_LS1043A
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default 2
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help
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This is the divider that is used to derive DSPI clock from Platform
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PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
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config SYS_FSL_DUART_CLK_DIV
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int "DUART clock divider"
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default 1 if ARCH_LS1043A
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default 2
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help
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This is the divider that is used to derive DUART clock from Platform
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clock, in another word DUART_clk = Platform_clk / this_divider.
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config SYS_FSL_I2C_CLK_DIV
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int "I2C clock divider"
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default 1 if ARCH_LS1043A
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default 2
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help
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This is the divider that is used to derive I2C clock from Platform
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clock, in another word I2C_clk = Platform_clk / this_divider.
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config SYS_FSL_IFC_CLK_DIV
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int "IFC clock divider"
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default 1 if ARCH_LS1043A
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default 2
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help
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This is the divider that is used to derive IFC clock from Platform
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clock, in another word IFC_clk = Platform_clk / this_divider.
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config SYS_FSL_LPUART_CLK_DIV
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int "LPUART clock divider"
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default 1 if ARCH_LS1043A
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default 2
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help
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This is the divider that is used to derive LPUART clock from Platform
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clock, in another word LPUART_clk = Platform_clk / this_divider.
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config SYS_FSL_SDHC_CLK_DIV
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int "SDHC clock divider"
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default 1 if ARCH_LS1043A
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default 1 if ARCH_LS1012A
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default 2
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help
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This is the divider that is used to derive SDHC clock from Platform
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clock, in another word SDHC_clk = Platform_clk / this_divider.
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endmenu
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config SYS_FSL_ERRATUM_A008336
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bool
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config SYS_FSL_ERRATUM_A008514
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bool
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config SYS_FSL_ERRATUM_A008585
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bool
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config SYS_FSL_ERRATUM_A008850
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bool
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config SYS_FSL_ERRATUM_A009635
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bool
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config SYS_FSL_ERRATUM_A009660
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bool
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config SYS_FSL_ERRATUM_A009929
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bool
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