upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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80 lines
2.3 KiB
80 lines
2.3 KiB
/*
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <ppc_asm.tmpl>
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#include <asm/mmu.h>
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#include <config.h>
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/**************************************************************************
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* TLB TABLE
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*
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* This table is used by the cpu boot code to setup the initial tlb
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* entries. Rather than make broad assumptions in the cpu source tree,
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* this table lets each board set things up however they like.
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*
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* Pointer to the table is returned in r1
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*
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*************************************************************************/
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.section .bootpg,"ax"
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.globl tlbtab
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tlbtab:
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tlbtab_start
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/*
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* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
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* speed up boot process. It is patched after relocation to enable SA_I
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*/
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tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_RWX | SA_G )
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/*
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* TLB entries for SDRAM are not needed on this platform. They are
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* generated dynamically in the SPD DDR2 detection routine.
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*/
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#ifdef CONFIG_SYS_INIT_RAM_DCACHE
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/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
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tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0,
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AC_RWX | SA_G )
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#endif
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/* TLB-entry for PCI Memory */
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tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x00000000, SZ_256M,
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CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_RW | SA_IG )
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tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x10000000, SZ_256M,
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CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_RW | SA_IG )
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tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x20000000, SZ_256M,
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CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_RW | SA_IG )
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tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x30000000, SZ_256M,
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CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_RW | SA_IG )
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/* TLB-entry for EBC */
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tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RW | SA_IG )
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/* TLB-entry for Internal Registers & OCM */
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/* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */
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tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_RWX | SA_I )
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/*TLB-entry PCI registers*/
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tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RW | SA_IG )
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/* TLB-entry for peripherals */
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tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RW | SA_IG)
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/* TLB-entry PCI IO Space - from sr@denx.de */
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tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RW | SA_IG)
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tlbtab_end
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#if defined(CONFIG_KORAT_PERMANENT)
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.globl korat_branch_absolute
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korat_branch_absolute:
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mtlr r3
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blr
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#endif
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