upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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61 lines
1.1 KiB
61 lines
1.1 KiB
/*
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* U-boot - cache.c
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*
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* Copyright (c) 2005-2008 Analog Devices Inc.
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*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <asm/blackfin.h>
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#include <asm/mach-common/bits/mpu.h>
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void flush_cache(unsigned long addr, unsigned long size)
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{
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/* no need to flush stuff in on chip memory (L1/L2/etc...) */
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if (addr >= 0xE0000000)
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return;
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if (icache_status())
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blackfin_icache_flush_range((void *)addr, (void *)(addr + size));
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if (dcache_status())
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blackfin_dcache_flush_range((void *)addr, (void *)(addr + size));
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}
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void icache_enable(void)
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{
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bfin_write_IMEM_CONTROL(IMC | ENICPLB);
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SSYNC();
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}
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void icache_disable(void)
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{
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bfin_write_IMEM_CONTROL(0);
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SSYNC();
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}
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int icache_status(void)
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{
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return bfin_read_IMEM_CONTROL() & IMC;
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}
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void dcache_enable(void)
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{
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bfin_write_DMEM_CONTROL(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
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SSYNC();
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}
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void dcache_disable(void)
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{
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bfin_write_DMEM_CONTROL(0);
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SSYNC();
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}
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int dcache_status(void)
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{
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return bfin_read_DMEM_CONTROL() & ACACHE_BCACHE;
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}
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