upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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141 lines
5.7 KiB
141 lines
5.7 KiB
/*
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* K2HK: SoC definitions
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_HARDWARE_K2HK_H
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#define __ASM_ARCH_HARDWARE_K2HK_H
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#define K2HK_PLL_CNTRL_BASE 0x02310000
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#define CLOCK_BASE K2HK_PLL_CNTRL_BASE
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#define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8)
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#define KS2_RSTCTRL_KEY 0x5a69
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#define KS2_RSTCTRL_MASK 0xffff0000
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#define KS2_RSTCTRL_SWRST 0xfffe0000
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#define K2HK_PSC_BASE 0x02350000
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#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
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#define JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
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#define K2HK_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
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#define K2HK_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
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#define ARM_PLL_EN BIT(13)
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#define K2HK_SPI0_BASE 0x21000400
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#define K2HK_SPI1_BASE 0x21000600
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#define K2HK_SPI2_BASE 0x21000800
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#define K2HK_SPI_BASE K2HK_SPI0_BASE
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/* Chip configuration unlock codes and registers */
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#define KEYSTONE_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
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#define KEYSTONE_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
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#define KEYSTONE_KICK0_MAGIC 0x83e70b13
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#define KEYSTONE_KICK1_MAGIC 0x95a4f1e0
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/* PA SS Registers */
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#define KS2_PASS_BASE 0x02000000
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/* PLL control registers */
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#define K2HK_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
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#define K2HK_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
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#define K2HK_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
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#define K2HK_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
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#define K2HK_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
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#define K2HK_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
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#define K2HK_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
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#define K2HK_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
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#define K2HK_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
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#define K2HK_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
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/* Power and Sleep Controller (PSC) Domains */
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#define K2HK_LPSC_MOD 0
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#define K2HK_LPSC_DUMMY1 1
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#define K2HK_LPSC_USB 2
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#define K2HK_LPSC_EMIF25_SPI 3
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#define K2HK_LPSC_TSIP 4
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#define K2HK_LPSC_DEBUGSS_TRC 5
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#define K2HK_LPSC_TETB_TRC 6
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#define K2HK_LPSC_PKTPROC 7
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#define KS2_LPSC_PA K2HK_LPSC_PKTPROC
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#define K2HK_LPSC_SGMII 8
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#define KS2_LPSC_CPGMAC K2HK_LPSC_SGMII
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#define K2HK_LPSC_CRYPTO 9
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#define K2HK_LPSC_PCIE 10
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#define K2HK_LPSC_SRIO 11
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#define K2HK_LPSC_VUSR0 12
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#define K2HK_LPSC_CHIP_SRSS 13
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#define K2HK_LPSC_MSMC 14
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#define K2HK_LPSC_GEM_0 15
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#define K2HK_LPSC_GEM_1 16
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#define K2HK_LPSC_GEM_2 17
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#define K2HK_LPSC_GEM_3 18
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#define K2HK_LPSC_GEM_4 19
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#define K2HK_LPSC_GEM_5 20
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#define K2HK_LPSC_GEM_6 21
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#define K2HK_LPSC_GEM_7 22
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#define K2HK_LPSC_EMIF4F_DDR3A 23
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#define K2HK_LPSC_EMIF4F_DDR3B 24
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#define K2HK_LPSC_TAC 25
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#define K2HK_LPSC_RAC 26
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#define K2HK_LPSC_RAC_1 27
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#define K2HK_LPSC_FFTC_A 28
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#define K2HK_LPSC_FFTC_B 29
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#define K2HK_LPSC_FFTC_C 30
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#define K2HK_LPSC_FFTC_D 31
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#define K2HK_LPSC_FFTC_E 32
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#define K2HK_LPSC_FFTC_F 33
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#define K2HK_LPSC_AI2 34
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#define K2HK_LPSC_TCP3D_0 35
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#define K2HK_LPSC_TCP3D_1 36
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#define K2HK_LPSC_TCP3D_2 37
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#define K2HK_LPSC_TCP3D_3 38
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#define K2HK_LPSC_VCP2X4_A 39
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#define K2HK_LPSC_CP2X4_B 40
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#define K2HK_LPSC_VCP2X4_C 41
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#define K2HK_LPSC_VCP2X4_D 42
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#define K2HK_LPSC_VCP2X4_E 43
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#define K2HK_LPSC_VCP2X4_F 44
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#define K2HK_LPSC_VCP2X4_G 45
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#define K2HK_LPSC_VCP2X4_H 46
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#define K2HK_LPSC_BCP 47
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#define K2HK_LPSC_DXB 48
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#define K2HK_LPSC_VUSR1 49
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#define K2HK_LPSC_XGE 50
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#define K2HK_LPSC_ARM_SREFLEX 51
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#define K2HK_LPSC_TETRIS 52
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/* DDR3A definitions */
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#define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000
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#define K2HK_DDR3A_EMIF_DATA_BASE 0x80000000
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#define K2HK_DDR3A_DDRPHYC 0x02329000
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/* DDR3B definitions */
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#define K2HK_DDR3B_EMIF_CTRL_BASE 0x21020000
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#define K2HK_DDR3B_EMIF_DATA_BASE 0x60000000
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#define K2HK_DDR3B_DDRPHYC 0x02328000
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/* Queue manager */
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#define DEVICE_QM_MANAGER_BASE 0x02a02000
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#define DEVICE_QM_DESC_SETUP_BASE 0x02a03000
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#define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a80000
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#define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
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#define DEVICE_QM_QUEUE_STATUS_BASE 0x02a40000
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#define DEVICE_QM_NUM_LINKRAMS 2
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#define DEVICE_QM_NUM_MEMREGIONS 20
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#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE 0x02004000
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#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400
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#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800
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#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000
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#define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24
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#define DEVICE_PA_CDMA_RX_NUM_FLOWS 32
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#define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9
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/* MSMC control */
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#define K2HK_MSMC_CTRL_BASE 0x0bc00000
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#endif /* __ASM_ARCH_HARDWARE_H */
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