upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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131 lines
3.0 KiB
131 lines
3.0 KiB
/*
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* Jz4740 UART support
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* Copyright (c) 2011
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* Qi Hardware, Xiangfu Liu <xiangfu@sharism.cc>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/jz4740.h>
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#include <serial.h>
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#include <linux/compiler.h>
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/*
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* serial_init - initialize a channel
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*
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* This routine initializes the number of data bits, parity
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* and set the selected baud rate. Interrupts are disabled.
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* Set the modem control signals if the option is selected.
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*
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* RETURNS: N/A
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*/
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struct jz4740_uart *uart = (struct jz4740_uart *)CONFIG_SYS_UART_BASE;
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static int jz_serial_init(void)
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{
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/* Disable port interrupts while changing hardware */
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writeb(0, &uart->dlhr_ier);
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/* Disable UART unit function */
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writeb(~UART_FCR_UUE, &uart->iir_fcr);
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/* Set both receiver and transmitter in UART mode (not SIR) */
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writeb(~(SIRCR_RSIRE | SIRCR_TSIRE), &uart->isr);
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/*
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* Set databits, stopbits and parity.
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* (8-bit data, 1 stopbit, no parity)
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*/
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writeb(UART_LCR_WLEN_8 | UART_LCR_STOP_1, &uart->lcr);
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/* Set baud rate */
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serial_setbrg();
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/* Enable UART unit, enable and clear FIFO */
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writeb(UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS,
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&uart->iir_fcr);
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return 0;
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}
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static void jz_serial_setbrg(void)
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{
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u32 baud_div, tmp;
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baud_div = CONFIG_SYS_EXTAL / 16 / CONFIG_BAUDRATE;
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tmp = readb(&uart->lcr);
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tmp |= UART_LCR_DLAB;
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writeb(tmp, &uart->lcr);
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writeb((baud_div >> 8) & 0xff, &uart->dlhr_ier);
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writeb(baud_div & 0xff, &uart->rbr_thr_dllr);
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tmp &= ~UART_LCR_DLAB;
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writeb(tmp, &uart->lcr);
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}
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static int jz_serial_tstc(void)
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{
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if (readb(&uart->lsr) & UART_LSR_DR)
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return 1;
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return 0;
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}
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static void jz_serial_putc(const char c)
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{
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if (c == '\n')
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serial_putc('\r');
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/* Wait for fifo to shift out some bytes */
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while (!((readb(&uart->lsr) & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60))
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;
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writeb((u8)c, &uart->rbr_thr_dllr);
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}
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static int jz_serial_getc(void)
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{
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while (!serial_tstc())
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;
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return readb(&uart->rbr_thr_dllr);
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}
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static struct serial_device jz_serial_drv = {
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.name = "jz_serial",
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.start = jz_serial_init,
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.stop = NULL,
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.setbrg = jz_serial_setbrg,
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.putc = jz_serial_putc,
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.puts = default_serial_puts,
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.getc = jz_serial_getc,
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.tstc = jz_serial_tstc,
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};
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void jz_serial_initialize(void)
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{
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serial_register(&jz_serial_drv);
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}
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__weak struct serial_device *default_serial_console(void)
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{
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return &jz_serial_drv;
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}
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