upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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162 lines
3.3 KiB
162 lines
3.3 KiB
/*
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* Copyright (c) 2006
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* Ingenic Semiconductor, <jlwei@ingenic.cn>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/jz4740.h>
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#define TIMER_CHAN 0
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#define TIMER_FDATA 0xffff /* Timer full data value */
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DECLARE_GLOBAL_DATA_PTR;
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static struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
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void reset_timer_masked(void)
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{
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/* reset time */
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gd->arch.lastinc = readl(&tcu->tcnt0);
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gd->arch.tbl = 0;
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}
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ulong get_timer_masked(void)
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{
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ulong now = readl(&tcu->tcnt0);
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if (gd->arch.lastinc <= now)
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gd->arch.tbl += now - gd->arch.lastinc; /* normal mode */
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else {
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/* we have an overflow ... */
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gd->arch.tbl += TIMER_FDATA + now - gd->arch.lastinc;
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}
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gd->arch.lastinc = now;
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return gd->arch.tbl;
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}
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void udelay_masked(unsigned long usec)
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{
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ulong tmo;
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ulong endtime;
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signed long diff;
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/* normalize */
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if (usec >= 1000) {
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tmo = usec / 1000;
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tmo *= CONFIG_SYS_HZ;
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tmo /= 1000;
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} else {
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if (usec > 1) {
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tmo = usec * CONFIG_SYS_HZ;
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tmo /= 1000*1000;
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} else
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tmo = 1;
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}
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endtime = get_timer_masked() + tmo;
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do {
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ulong now = get_timer_masked();
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diff = endtime - now;
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} while (diff >= 0);
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}
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int timer_init(void)
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{
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writel(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0);
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writel(0, &tcu->tcnt0);
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writel(0, &tcu->tdhr0);
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writel(TIMER_FDATA, &tcu->tdfr0);
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/* mask irqs */
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writel((1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)), &tcu->tmsr);
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writel(1 << TIMER_CHAN, &tcu->tscr); /* enable timer clock */
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writeb(1 << TIMER_CHAN, &tcu->tesr); /* start counting up */
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gd->arch.lastinc = 0;
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gd->arch.tbl = 0;
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return 0;
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}
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void reset_timer(void)
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{
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reset_timer_masked();
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}
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ulong get_timer(ulong base)
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{
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return get_timer_masked() - base;
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}
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void set_timer(ulong t)
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{
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gd->arch.tbl = t;
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}
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void __udelay(unsigned long usec)
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{
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ulong tmo, tmp;
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/* normalize */
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if (usec >= 1000) {
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tmo = usec / 1000;
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tmo *= CONFIG_SYS_HZ;
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tmo /= 1000;
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} else {
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if (usec >= 1) {
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tmo = usec * CONFIG_SYS_HZ;
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tmo /= 1000 * 1000;
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} else
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tmo = 1;
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}
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/* check for rollover during this delay */
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tmp = get_timer(0);
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if ((tmp + tmo) < tmp)
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reset_timer_masked(); /* timer would roll over */
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else
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tmo += tmp;
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while (get_timer_masked() < tmo)
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;
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On MIPS it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On MIPS it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return CONFIG_SYS_HZ;
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}
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