upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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114 lines
2.9 KiB
114 lines
2.9 KiB
/*
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* (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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* (C) Copyright 2011, Julius Baxter <julius@opencores.org>
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/system.h>
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#include <asm/openrisc_exc.h>
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static ulong timestamp;
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/* how many counter cycles in a jiffy */
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#define TIMER_COUNTER_CYCLES (CONFIG_SYS_CLK_FREQ/CONFIG_SYS_OPENRISC_TMR_HZ)
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/* how many ms elapses between each timer interrupt */
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#define TIMER_TIMESTAMP_INC (1000/CONFIG_SYS_OPENRISC_TMR_HZ)
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/* how many cycles per ms */
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#define TIMER_CYCLES_MS (CONFIG_SYS_CLK_FREQ/1000)
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/* how many cycles per us */
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#define TIMER_CYCLES_US (CONFIG_SYS_CLK_FREQ/1000000uL)
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void timer_isr(void)
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{
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timestamp += TIMER_TIMESTAMP_INC;
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mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
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(TIMER_COUNTER_CYCLES & SPR_TTMR_TP));
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}
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int timer_init(void)
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{
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/* Install timer exception handler */
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exception_install_handler(EXC_TIMER, timer_isr);
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/* Set up the timer for the first expiration. */
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timestamp = 0;
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mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
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(TIMER_COUNTER_CYCLES & SPR_TTMR_TP));
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/* Enable tick timer exception in supervisor register */
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_TEE);
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return 0;
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}
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void reset_timer(void)
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{
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timestamp = 0;
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mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
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(TIMER_COUNTER_CYCLES & SPR_TTMR_TP));
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}
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/*
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* The timer value in ms is calculated by taking the
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* value accumulated by full timer revolutions plus the value
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* accumulated in this period
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*/
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ulong get_timer(ulong base)
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{
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return timestamp + mfspr(SPR_TTCR)/TIMER_CYCLES_MS - base;
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}
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void set_timer(ulong t)
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{
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reset_timer();
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timestamp = t;
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}
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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ulong get_tbclk(void)
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{
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return CONFIG_SYS_HZ;
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}
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void __udelay(ulong usec)
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{
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ulong elapsed = 0;
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ulong tick;
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ulong last_tick;
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last_tick = mfspr(SPR_TTCR);
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while ((elapsed / TIMER_CYCLES_US) < usec) {
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tick = mfspr(SPR_TTCR);
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if (tick >= last_tick)
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elapsed += (tick - last_tick);
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else
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elapsed += TIMER_COUNTER_CYCLES - (last_tick - tick);
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last_tick = tick;
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}
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}
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