upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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231 lines
6.8 KiB
231 lines
6.8 KiB
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* Configuration settings for the phytec PCM-052 SoM.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/imx-regs.h>
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#define CONFIG_VF610
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#define CONFIG_SYS_GENERIC_BOARD
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_SYS_THUMB_BUILD
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/* Enable passing of ATAGs */
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#define CONFIG_CMDLINE_TAG
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_FSL_LPUART
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#define LPUART_BASE UART1_BASE
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/* Allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SYS_UART_PORT (1)
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#define CONFIG_BAUDRATE 115200
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#undef CONFIG_CMD_IMLS
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/* NAND support */
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_NAND_TRIMFFS
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_USE_ARCH_MEMCPY
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
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#define CONFIG_JFFS2_NAND
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/* UBI */
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#define CONFIG_CMD_UBI
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#define CONFIG_CMD_UBIFS
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#define CONFIG_RBTREE
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#define CONFIG_LZO
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/* Dynamic MTD partition support */
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_MTD_PARTITIONS
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#define CONFIG_MTD_DEVICE
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#define MTDIDS_DEFAULT "nand0=NAND,nor0=qspi0-a,nor1=qspi0-b"
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#define MTDPARTS_DEFAULT "mtdparts=NAND:256k(spare)"\
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",384k(bootloader)"\
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",128k(env1)"\
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",128k(env2)"\
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",3840k(kernel)"\
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",-(rootfs)"\
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",qspi0-a:-(jffs2),qspio0-b:-(jffs2)"
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#endif
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#define CONFIG_MMC
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_FSL_ESDHC_NUM 1
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/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
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#define CONFIG_CMD_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_CMD_FAT
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_MII
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#define CONFIG_FEC_MXC
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#define CONFIG_MII
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL
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/* QSPI Configs*/
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#define CONFIG_FSL_QSPI
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#ifdef CONFIG_FSL_QSPI
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#define CONFIG_CMD_SF
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_STMICRO
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#define FSL_QSPI_FLASH_SIZE (1 << 24)
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#define FSL_QSPI_FLASH_NUM 2
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#define CONFIG_SYS_FSL_QSPI_LE
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#endif
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/* I2C Configs */
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#define CONFIG_CMD_I2C
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC_I2C3
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#define CONFIG_SYS_I2C_MXC
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/* RTC (actually an RV-4162 but M41T62-compatible) */
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#define CONFIG_CMD_DATE
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#define CONFIG_RTC_M41T62
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#define CONFIG_SYS_RTC_BUS_NUM 2
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/* EEPROM (24FC256) */
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#define CONFIG_CMD_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_I2C_EEPROM_BUS 2
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_LOADADDR 0x82000000
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/* We boot from the gfxRAM area of the OCRAM. */
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#define CONFIG_SYS_TEXT_BASE 0x3f408000
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#define CONFIG_BOARD_SIZE_LIMIT 524288
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#define CONFIG_BOOTCOMMAND "run bootcmd_sd"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootfile=uImage\0" \
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"bootargs_base=setenv bootargs rw mem=256M " \
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"console=ttymxc1,115200n8\0" \
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"bootargs_sd=setenv bootargs ${bootargs} " \
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"root=/dev/mmcblk0p2 rootwait\0" \
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"bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \
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"nfsroot=${serverip}:${nfs_root},v3,tcp\0" \
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"bootargs_nand=setenv bootargs ${bootargs} " \
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"root=/dev/mtdblock2 rootfstype=jffs2\0" \
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"bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
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"bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; mmc rescan; " \
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"fatload mmc 0:1 ${loadaddr} ${bootfile}; bootm ${loadaddr}\0" \
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"bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \
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"tftpboot ${loadaddr} ${tftploc}${bootfile}; bootm\0" \
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"bootcmd_nand='run bootargs_base bootargs_nand bootargs_mtd; " \
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"nand read ${loadaddr} 0x000E0000 0x3C0000; " \
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"bootm ${loadaddr}\0" \
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"tftploc=/path/to/tftp/directory/\0" \
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"nfs_root=/path/to/nfs/root\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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"update_kernel_from_sd=mw.b $(loadaddr) 0xff 0x3C0000; " \
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"mmc rescan; fatload mmc 0:2 ${loadaddr} ${bootfile}; " \
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"nand erase 0xE0000 0x3C0000; " \
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"nand write.i ${loadaddr} 0xE0000 0x3C0000\0" \
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"update_rootfs_from_tftp=mw.b ${loadaddr} 0xff 0x8F20000; " \
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"tftp ${loadaddr} ${tftp}${filesys}; " \
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"nand erase 0x4A0000 0x8F20000; " \
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"nand write.i ${loadaddr} 0x4A0000 0x8F20000\0" \
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"filesys=rootfs.jffs2\0"
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/* miscellaneous commands */
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#define CONFIG_CMD_ELF
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_CMD_MEMTEST
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#define CONFIG_SYS_MEMTEST_START 0x80010000
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#define CONFIG_SYS_MEMTEST_END 0x87C00000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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/*
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* Stack sizes
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
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/* Physical memory map */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM (0x80000000)
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#define PHYS_SDRAM_SIZE (256 * 1024 * 1024)
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* FLASH and environment organization */
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#define CONFIG_SYS_NO_FLASH
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#ifdef CONFIG_ENV_IS_IN_MMC
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#define CONFIG_ENV_SIZE (8 * 1024)
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#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#endif
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#ifdef CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_SECT_SIZE (128 * 1024)
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#define CONFIG_ENV_SIZE (8 * 1024)
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#define CONFIG_ENV_OFFSET 0x80000
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#define CONFIG_ENV_SIZE_REDUND (8 * 1024)
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#define CONFIG_ENV_OFFSET_REDUND 0xA0000
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#endif
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#define CONFIG_OF_LIBFDT
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#define CONFIG_CMD_BOOTZ
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#endif
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