upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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485 lines
12 KiB
485 lines
12 KiB
/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#include <malloc.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <miiphy.h>
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#include <phy.h>
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#include "../common/ngpixis.h"
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#include "../common/fman.h"
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#include <asm/fsl_dtsec.h>
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#define EMI_NONE 0xffffffff
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#define EMI_MASK 0xf0000000
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#define EMI1_RGMII 0x0
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#define EMI1_SLOT3 0x80000000 /* bank1 EFGH */
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#define EMI1_SLOT4 0x40000000 /* bank2 ABCD */
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#define EMI1_SLOT5 0xc0000000 /* bank3 ABCD */
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#define EMI2_SLOT4 0x10000000 /* bank2 ABCD */
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#define EMI2_SLOT5 0x30000000 /* bank3 ABCD */
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#define EMI1_MASK 0xc0000000
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#define EMI2_MASK 0x30000000
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static int mdio_mux[NUM_FM_PORTS];
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static char *mdio_names[16] = {
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"P4080DS_MDIO0",
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"P4080DS_MDIO1",
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NULL,
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"P4080DS_MDIO3",
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"P4080DS_MDIO4",
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NULL, NULL, NULL,
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"P4080DS_MDIO8",
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NULL, NULL, NULL,
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"P4080DS_MDIO12",
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NULL, NULL, NULL,
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};
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/*
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* Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
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* that the mapping must be determined dynamically, or that the lane maps to
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* something other than a board slot.
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*/
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static u8 lane_to_slot[] = {
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1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5
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};
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static char *p4080ds_mdio_name_for_muxval(u32 muxval)
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{
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return mdio_names[(muxval & EMI_MASK) >> 28];
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}
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struct mii_dev *mii_dev_for_muxval(u32 muxval)
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{
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struct mii_dev *bus;
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char *name = p4080ds_mdio_name_for_muxval(muxval);
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if (!name) {
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printf("No bus for muxval %x\n", muxval);
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return NULL;
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}
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bus = miiphy_get_dev_by_name(name);
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if (!bus) {
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printf("No bus by name %s\n", name);
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return NULL;
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}
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return bus;
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}
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#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS)
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int board_phy_config(struct phy_device *phydev)
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{
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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if (phydev->drv->uid == PHY_UID_TN2020) {
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unsigned long timeout = 1 * 1000; /* 1 seconds */
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enum srds_prtcl device;
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/*
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* Wait for the XAUI to come out of reset. This is when it
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* starts transmitting alignment signals.
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*/
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while (--timeout) {
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int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1);
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if (reg < 0) {
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printf("TN2020: Error reading from PHY at "
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"address %u\n", phydev->addr);
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break;
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}
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/*
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* Note that we've never actually seen
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* MDIO_CTRL1_RESET set to 1.
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*/
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if ((reg & MDIO_CTRL1_RESET) == 0)
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break;
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udelay(1000);
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}
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if (!timeout) {
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printf("TN2020: Timeout waiting for PHY at address %u "
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" to reset.\n", phydev->addr);
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}
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switch (phydev->addr) {
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case CONFIG_SYS_FM1_10GEC1_PHY_ADDR:
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device = XAUI_FM1;
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break;
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case CONFIG_SYS_FM2_10GEC1_PHY_ADDR:
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device = XAUI_FM2;
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break;
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default:
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device = NONE;
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}
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serdes_reset_rx(device);
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}
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return 0;
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}
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#endif
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struct p4080ds_mdio {
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u32 muxval;
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struct mii_dev *realbus;
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};
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static void p4080ds_mux_mdio(u32 muxval)
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{
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ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
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uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK);
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gpioval |= muxval;
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out_be32(&pgpio->gpdat, gpioval);
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}
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static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad,
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int regnum)
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{
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struct p4080ds_mdio *priv = bus->priv;
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p4080ds_mux_mdio(priv->muxval);
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return priv->realbus->read(priv->realbus, addr, devad, regnum);
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}
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static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad,
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int regnum, u16 value)
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{
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struct p4080ds_mdio *priv = bus->priv;
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p4080ds_mux_mdio(priv->muxval);
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return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
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}
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static int p4080ds_mdio_reset(struct mii_dev *bus)
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{
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struct p4080ds_mdio *priv = bus->priv;
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return priv->realbus->reset(priv->realbus);
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}
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static int p4080ds_mdio_init(char *realbusname, u32 muxval)
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{
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struct p4080ds_mdio *pmdio;
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate P4080DS MDIO bus\n");
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return -1;
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}
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pmdio = malloc(sizeof(*pmdio));
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if (!pmdio) {
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printf("Failed to allocate P4080DS private data\n");
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free(bus);
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return -1;
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}
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bus->read = p4080ds_mdio_read;
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bus->write = p4080ds_mdio_write;
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bus->reset = p4080ds_mdio_reset;
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sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval));
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pmdio->realbus = miiphy_get_dev_by_name(realbusname);
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if (!pmdio->realbus) {
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printf("No bus with name %s\n", realbusname);
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free(bus);
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free(pmdio);
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return -1;
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}
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pmdio->muxval = muxval;
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bus->priv = pmdio;
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return mdio_register(bus);
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}
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void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
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enum fm_port port, int offset)
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{
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if (mdio_mux[port] == EMI1_RGMII)
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fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
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if (mdio_mux[port] == EMI1_SLOT3) {
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int idx = port - FM2_DTSEC1 + 5;
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char phy[16];
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sprintf(phy, "phy%d_slot3", idx);
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fdt_set_phy_handle(blob, prop, pa, phy);
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}
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}
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void fdt_fixup_board_enet(void *fdt)
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{
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int i;
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/*
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* P4080DS can be configured in many different ways, supporting a number
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* of combinations of ethernet devices and phy types. In order to
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* have just one device tree for all of those configurations, we fix up
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* the tree here. By default, the device tree configures FM1 and FM2
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* for SGMII, and configures XAUI on both 10G interfaces. So we have
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* a number of different variables to track:
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*
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* 1) Whether the device is configured at all. Whichever devices are
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* not enabled should be disabled by setting the "status" property
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* to "disabled".
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* 2) What the PHY interface is. If this is an RGMII connection,
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* we should change the "phy-connection-type" property to
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* "rgmii"
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* 3) Which PHY is being used. Because the MDIO buses are muxed,
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* we need to redirect the "phy-handle" property to point at the
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* PHY on the right slot/bus.
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*/
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/* We've got six MDIO nodes that may or may not need to exist */
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fdt_status_disabled_by_alias(fdt, "emi1_slot3");
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fdt_status_disabled_by_alias(fdt, "emi1_slot4");
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fdt_status_disabled_by_alias(fdt, "emi1_slot5");
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fdt_status_disabled_by_alias(fdt, "emi2_slot4");
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fdt_status_disabled_by_alias(fdt, "emi2_slot5");
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for (i = 0; i < NUM_FM_PORTS; i++) {
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switch (mdio_mux[i]) {
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case EMI1_SLOT3:
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fdt_status_okay_by_alias(fdt, "emi1_slot3");
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break;
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case EMI1_SLOT4:
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fdt_status_okay_by_alias(fdt, "emi1_slot4");
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break;
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case EMI1_SLOT5:
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fdt_status_okay_by_alias(fdt, "emi1_slot5");
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break;
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case EMI2_SLOT4:
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fdt_status_okay_by_alias(fdt, "emi2_slot4");
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break;
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case EMI2_SLOT5:
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fdt_status_okay_by_alias(fdt, "emi2_slot5");
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break;
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}
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}
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}
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_FMAN_ENET
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ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
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int i;
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struct fsl_pq_mdio_info dtsec_mdio_info;
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struct tgec_mdio_info tgec_mdio_info;
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/* Initialize the mdio_mux array so we can recognize empty elements */
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for (i = 0; i < NUM_FM_PORTS; i++)
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mdio_mux[i] = EMI_NONE;
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/* The first 4 GPIOs are outputs to control MDIO bus muxing */
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out_be32(&pgpio->gpdir, EMI_MASK);
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dtsec_mdio_info.regs =
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(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
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dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
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/* Register the 1G MDIO bus */
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fsl_pq_mdio_init(bis, &dtsec_mdio_info);
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tgec_mdio_info.regs =
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(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
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tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
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/* Register the 10G MDIO bus */
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fm_tgec_mdio_init(bis, &tgec_mdio_info);
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/* Register the 6 muxing front-ends to the MDIO buses */
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p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
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p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
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p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
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p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
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p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4);
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p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5);
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fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
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fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
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#if (CONFIG_SYS_NUM_FMAN == 2)
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fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR);
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fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR);
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fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
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#endif
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for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
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int idx = i - FM1_DTSEC1, lane, slot;
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_SGMII:
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lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
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if (lane < 0)
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break;
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slot = lane_to_slot[lane];
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switch (slot) {
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case 3:
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mdio_mux[i] = EMI1_SLOT3;
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fm_info_set_mdio(i,
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mii_dev_for_muxval(mdio_mux[i]));
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break;
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case 4:
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mdio_mux[i] = EMI1_SLOT4;
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fm_info_set_mdio(i,
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mii_dev_for_muxval(mdio_mux[i]));
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break;
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case 5:
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mdio_mux[i] = EMI1_SLOT5;
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fm_info_set_mdio(i,
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mii_dev_for_muxval(mdio_mux[i]));
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break;
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};
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break;
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case PHY_INTERFACE_MODE_RGMII:
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fm_info_set_phy_address(i, 0);
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mdio_mux[i] = EMI1_RGMII;
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fm_info_set_mdio(i,
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mii_dev_for_muxval(mdio_mux[i]));
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break;
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default:
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break;
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}
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}
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for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
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int idx = i - FM1_10GEC1, lane, slot;
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_XGMII:
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lane = serdes_get_first_lane(XAUI_FM1 + idx);
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if (lane < 0)
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break;
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slot = lane_to_slot[lane];
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switch (slot) {
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case 4:
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mdio_mux[i] = EMI2_SLOT4;
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fm_info_set_mdio(i,
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mii_dev_for_muxval(mdio_mux[i]));
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break;
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case 5:
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mdio_mux[i] = EMI2_SLOT5;
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fm_info_set_mdio(i,
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mii_dev_for_muxval(mdio_mux[i]));
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break;
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};
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break;
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default:
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break;
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}
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}
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#if (CONFIG_SYS_NUM_FMAN == 2)
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for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
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int idx = i - FM2_DTSEC1, lane, slot;
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_SGMII:
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lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
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if (lane < 0)
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break;
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slot = lane_to_slot[lane];
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switch (slot) {
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case 3:
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mdio_mux[i] = EMI1_SLOT3;
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fm_info_set_mdio(i,
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mii_dev_for_muxval(mdio_mux[i]));
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break;
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case 4:
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mdio_mux[i] = EMI1_SLOT4;
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fm_info_set_mdio(i,
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mii_dev_for_muxval(mdio_mux[i]));
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break;
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case 5:
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mdio_mux[i] = EMI1_SLOT5;
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fm_info_set_mdio(i,
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mii_dev_for_muxval(mdio_mux[i]));
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break;
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};
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break;
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case PHY_INTERFACE_MODE_RGMII:
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fm_info_set_phy_address(i, 0);
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mdio_mux[i] = EMI1_RGMII;
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fm_info_set_mdio(i,
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mii_dev_for_muxval(mdio_mux[i]));
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break;
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default:
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break;
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}
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}
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for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
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int idx = i - FM2_10GEC1, lane, slot;
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_XGMII:
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lane = serdes_get_first_lane(XAUI_FM2 + idx);
|
|
if (lane < 0)
|
|
break;
|
|
slot = lane_to_slot[lane];
|
|
switch (slot) {
|
|
case 4:
|
|
mdio_mux[i] = EMI2_SLOT4;
|
|
fm_info_set_mdio(i,
|
|
mii_dev_for_muxval(mdio_mux[i]));
|
|
break;
|
|
case 5:
|
|
mdio_mux[i] = EMI2_SLOT5;
|
|
fm_info_set_mdio(i,
|
|
mii_dev_for_muxval(mdio_mux[i]));
|
|
break;
|
|
};
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
cpu_eth_init(bis);
|
|
#endif /* CONFIG_FMAN_ENET */
|
|
|
|
return pci_eth_init(bis);
|
|
}
|
|
|