upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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106 lines
2.6 KiB
106 lines
2.6 KiB
/*
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* Copyright (C) 2010 Freescale Semiconductor, Inc.
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* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <i2c.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <pci.h>
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#include <mpc83xx.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_mpc83xx_serdes.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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printf("Board: MPC8308 P1M\n");
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return 0;
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}
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static struct pci_region pcie_regions_0[] = {
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{
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.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
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.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
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.size = CONFIG_SYS_PCIE1_MEM_SIZE,
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.flags = PCI_REGION_MEM,
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},
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{
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.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
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.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
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.size = CONFIG_SYS_PCIE1_IO_SIZE,
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.flags = PCI_REGION_IO,
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},
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};
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void pci_init_board(void)
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{
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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sysconf83xx_t *sysconf = &immr->sysconf;
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law83xx_t *pcie_law = sysconf->pcielaw;
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struct pci_region *pcie_reg[] = { pcie_regions_0 };
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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/* Deassert the resets in the control register */
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out_be32(&sysconf->pecr1, 0xE0008000);
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udelay(2000);
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/* Configure PCI Express Local Access Windows */
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out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
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out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
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mpc83xx_pcie_init(1, pcie_reg);
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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fdt_fixup_dr_usb(blob, bd);
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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int rv, num_if = 0;
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/* Initialize TSECs first */
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rv = cpu_eth_init(bis);
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if (rv >= 0)
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num_if += rv;
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else
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printf("ERROR: failed to initialize TSECs.\n");
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rv = pci_eth_init(bis);
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if (rv >= 0)
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num_if += rv;
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else
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printf("ERROR: failed to initialize PCI Ethernet.\n");
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return num_if;
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}
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