upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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319 lines
9.8 KiB
319 lines
9.8 KiB
/*
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* Porting to U-Boot:
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*
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* (C) Copyright 2010
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* Lattice's ispVME Embedded Tool to load Lattice's FPGA:
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*
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* Lattice Semiconductor Corp. Copyright 2009
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef _VME_OPCODE_H
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#define _VME_OPCODE_H
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#define VME_VERSION_NUMBER "12.1"
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/* Maximum declarations. */
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#define VMEHEXMAX 60000L /* The hex file is split 60K per file. */
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#define SCANMAX 64000L /* The maximum SDR/SIR burst. */
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/*
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*
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* Supported JTAG state transitions.
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*
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*/
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#define RESET 0x00
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#define IDLE 0x01
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#define IRPAUSE 0x02
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#define DRPAUSE 0x03
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#define SHIFTIR 0x04
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#define SHIFTDR 0x05
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/* 11/15/05 Nguyen changed to support DRCAPTURE*/
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#define DRCAPTURE 0x06
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/*
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* Flow control register bit definitions. A set bit indicates
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* that the register currently exhibits the corresponding mode.
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*/
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#define INTEL_PRGM 0x0001 /* Intelligent programming is in effect. */
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#define CASCADE 0x0002 /* Currently splitting large SDR. */
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#define REPEATLOOP 0x0008 /* Currently executing a repeat loop. */
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#define SHIFTRIGHT 0x0080 /* The next data stream needs a right shift. */
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#define SHIFTLEFT 0x0100 /* The next data stream needs a left shift. */
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#define VERIFYUES 0x0200 /* Continue if fail is in effect. */
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/*
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* DataType register bit definitions. A set bit indicates
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* that the register currently holds the corresponding type of data.
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*/
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#define EXPRESS 0x0001 /* Simultaneous program and verify. */
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#define SIR_DATA 0x0002 /* SIR is the active SVF command. */
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#define SDR_DATA 0x0004 /* SDR is the active SVF command. */
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#define COMPRESS 0x0008 /* Data is compressed. */
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#define TDI_DATA 0x0010 /* TDI data is present. */
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#define TDO_DATA 0x0020 /* TDO data is present. */
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#define MASK_DATA 0x0040 /* MASK data is present. */
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#define HEAP_IN 0x0080 /* Data is from the heap. */
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#define LHEAP_IN 0x0200 /* Data is from intel data buffer. */
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#define VARIABLE 0x0400 /* Data is from a declared variable. */
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#define CRC_DATA 0x0800 /* CRC data is pressent. */
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#define CMASK_DATA 0x1000 /* CMASK data is pressent. */
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#define RMASK_DATA 0x2000 /* RMASK data is pressent. */
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#define READ_DATA 0x4000 /* READ data is pressent. */
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#define DMASK_DATA 0x8000 /* DMASK data is pressent. */
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/*
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*
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* Pin opcodes.
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*
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*/
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#define signalENABLE 0x1C /* ispENABLE pin. */
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#define signalTMS 0x1D /* TMS pin. */
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#define signalTCK 0x1E /* TCK pin. */
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#define signalTDI 0x1F /* TDI pin. */
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#define signalTRST 0x20 /* TRST pin. */
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/*
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*
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* Supported vendors.
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*
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*/
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#define VENDOR 0x56
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#define LATTICE 0x01
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#define ALTERA 0x02
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#define XILINX 0x03
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/*
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* Opcode definitions.
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*
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* Note: opcodes must be unique.
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*/
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#define ENDDATA 0x00 /* The end of the current SDR data stream. */
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#define RUNTEST 0x01 /* The duration to stay at the stable state. */
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#define ENDDR 0x02 /* The stable state after SDR. */
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#define ENDIR 0x03 /* The stable state after SIR. */
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#define ENDSTATE 0x04 /* The stable state after RUNTEST. */
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#define TRST 0x05 /* Assert the TRST pin. */
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#define HIR 0x06 /*
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* The sum of the IR bits of the
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* leading devices.
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*/
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#define TIR 0x07 /*
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* The sum of the IR bits of the trailing
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* devices.
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*/
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#define HDR 0x08 /* The number of leading devices. */
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#define TDR 0x09 /* The number of trailing devices. */
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#define ispEN 0x0A /* Assert the ispEN pin. */
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#define FREQUENCY 0x0B /*
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* The maximum clock rate to run the JTAG state
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* machine.
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*/
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#define STATE 0x10 /* Move to the next stable state. */
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#define SIR 0x11 /* The instruction stream follows. */
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#define SDR 0x12 /* The data stream follows. */
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#define TDI 0x13 /* The following data stream feeds into
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the device. */
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#define TDO 0x14 /*
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* The following data stream is compared against
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* the device.
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*/
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#define MASK 0x15 /* The following data stream is used as mask. */
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#define XSDR 0x16 /*
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* The following data stream is for simultaneous
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* program and verify.
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*/
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#define XTDI 0x17 /* The following data stream is for shift in
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* only. It must be stored for the next
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* XSDR.
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*/
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#define XTDO 0x18 /*
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* There is not data stream. The data stream
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* was stored from the previous XTDI.
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*/
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#define MEM 0x19 /*
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* The maximum memory needed to allocate in
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* order hold one row of data.
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*/
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#define WAIT 0x1A /* The duration of delay to observe. */
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#define TCK 0x1B /* The number of TCK pulses. */
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#define SHR 0x23 /*
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* Set the flow control register for
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* right shift
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*/
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#define SHL 0x24 /*
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* Set the flow control register for left shift.
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*/
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#define HEAP 0x32 /* The memory size needed to hold one loop. */
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#define REPEAT 0x33 /* The beginning of the loop. */
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#define LEFTPAREN 0x35 /* The beginning of data following the loop. */
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#define VAR 0x55 /* Plac holder for loop data. */
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#define SEC 0x1C /*
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* The delay time in seconds that must be
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* observed.
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*/
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#define SMASK 0x1D /* The mask for TDI data. */
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#define MAX_WAIT 0x1E /* The absolute maximum wait time. */
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#define ON 0x1F /* Assert the targeted pin. */
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#define OFF 0x20 /* Dis-assert the targeted pin. */
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#define SETFLOW 0x30 /* Change the flow control register. */
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#define RESETFLOW 0x31 /* Clear the flow control register. */
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#define CRC 0x47 /*
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* The following data stream is used for CRC
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* calculation.
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*/
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#define CMASK 0x48 /*
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* The following data stream is used as mask
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* for CRC calculation.
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*/
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#define RMASK 0x49 /*
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* The following data stream is used as mask
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* for read and save.
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*/
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#define READ 0x50 /*
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* The following data stream is used for read
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* and save.
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*/
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#define ENDLOOP 0x59 /* The end of the repeat loop. */
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#define SECUREHEAP 0x60 /* Used to secure the HEAP opcode. */
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#define VUES 0x61 /* Support continue if fail. */
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#define DMASK 0x62 /*
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* The following data stream is used for dynamic
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* I/O.
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*/
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#define COMMENT 0x63 /* Support SVF comments in the VME file. */
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#define HEADER 0x64 /* Support header in VME file. */
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#define FILE_CRC 0x65 /* Support crc-protected VME file. */
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#define LCOUNT 0x66 /* Support intelligent programming. */
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#define LDELAY 0x67 /* Support intelligent programming. */
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#define LSDR 0x68 /* Support intelligent programming. */
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#define LHEAP 0x69 /*
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* Memory needed to hold intelligent data
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* buffer
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*/
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#define CONTINUE 0x70 /* Allow continuation. */
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#define LVDS 0x71 /* Support LVDS. */
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#define ENDVME 0x7F /* End of the VME file. */
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#define ENDFILE 0xFF /* End of file. */
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/*
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*
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* ispVM Embedded Return Codes.
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*
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*/
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#define VME_VERIFICATION_FAILURE -1
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#define VME_FILE_READ_FAILURE -2
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#define VME_VERSION_FAILURE -3
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#define VME_INVALID_FILE -4
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#define VME_ARGUMENT_FAILURE -5
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#define VME_CRC_FAILURE -6
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#define g_ucPinTDI 0x01
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#define g_ucPinTCK 0x02
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#define g_ucPinTMS 0x04
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#define g_ucPinENABLE 0x08
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#define g_ucPinTRST 0x10
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/*
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*
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* Type definitions.
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*
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*/
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/* Support LVDS */
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typedef struct {
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unsigned short usPositiveIndex;
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unsigned short usNegativeIndex;
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unsigned char ucUpdate;
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} LVDSPair;
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typedef enum {
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min_lattice_iface_type, /* insert all new types after this */
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lattice_jtag_mode, /* jtag/tap */
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max_lattice_iface_type /* insert all new types before this */
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} Lattice_iface;
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typedef enum {
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min_lattice_type,
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Lattice_XP2, /* Lattice XP2 Family */
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max_lattice_type /* insert all new types before this */
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} Lattice_Family;
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typedef struct {
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Lattice_Family family; /* part type */
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Lattice_iface iface; /* interface type */
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size_t size; /* bytes of data part can accept */
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void *iface_fns; /* interface function table */
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void *base; /* base interface address */
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int cookie; /* implementation specific cookie */
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char *desc; /* description string */
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} Lattice_desc; /* end, typedef Altera_desc */
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/* Lattice Model Type */
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#define CONFIG_SYS_XP2 CONFIG_SYS_FPGA_DEV(0x1)
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/* Board specific implementation specific function types */
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typedef void (*Lattice_jtag_init)(void);
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typedef void (*Lattice_jtag_set_tdi)(int v);
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typedef void (*Lattice_jtag_set_tms)(int v);
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typedef void (*Lattice_jtag_set_tck)(int v);
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typedef int (*Lattice_jtag_get_tdo)(void);
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typedef struct {
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Lattice_jtag_init jtag_init;
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Lattice_jtag_set_tdi jtag_set_tdi;
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Lattice_jtag_set_tms jtag_set_tms;
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Lattice_jtag_set_tck jtag_set_tck;
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Lattice_jtag_get_tdo jtag_get_tdo;
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} lattice_board_specific_func;
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void writePort(unsigned char pins, unsigned char value);
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unsigned char readPort(void);
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void sclock(void);
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void ispVMDelay(unsigned short int a_usMicroSecondDelay);
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void calibration(void);
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int lattice_load(Lattice_desc *desc, void *buf, size_t bsize);
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int lattice_dump(Lattice_desc *desc, void *buf, size_t bsize);
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int lattice_info(Lattice_desc *desc);
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void ispVMStart(void);
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void ispVMEnd(void);
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extern void ispVMFreeMem(void);
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signed char ispVMCode(void);
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void ispVMDelay(unsigned short int a_usMicroSecondDelay);
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void ispVMCalculateCRC32(unsigned char a_ucData);
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unsigned char GetByte(void);
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void writePort(unsigned char pins, unsigned char value);
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unsigned char readPort(void);
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void sclock(void);
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#endif
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