upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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213 lines
5.6 KiB
213 lines
5.6 KiB
/*
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* Board specific setup info
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*
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* (C) Copyright 2004, ARM Ltd.
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* Philippe Robin, <philippe.robin@arm.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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/* Reset using CM control register */
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.global reset_cpu
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reset_cpu:
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mov r0, #CM_BASE
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ldr r1,[r0,#OS_CTRL]
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orr r1,r1,#CMMASK_RESET
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str r1,[r0,#OS_CTRL]
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reset_failed:
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b reset_failed
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/* Set up the platform, once the cpu has been initialized */
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.globl lowlevel_init
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lowlevel_init:
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/* If U-Boot has been run after the ARM boot monitor
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* then all the necessary actions have been done
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* otherwise we are running from user flash mapped to 0x00000000
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* --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
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* Changes to the (possibly soft) reset defaults of the processor
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* itself should be performed in cpu/arm<>/start.S
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* This function affects only the core module or board settings
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*/
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#ifdef CONFIG_CM_INIT
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/* CM has an initialization register
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* - bits in it are wired into test-chip pins to force
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* reset defaults
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* - may need to change its contents for U-Boot
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*/
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/* set the desired CM specific value */
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mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */
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#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
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orr r2,r2,#CMMASK_INIT_102
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#else
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#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
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!defined (CONFIG_CM940T)
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#ifdef CONFIG_CM_MULTIPLE_SSRAM
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/* set simple mapping */
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and r2,r2,#CMMASK_MAP_SIMPLE
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#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */
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#ifdef CONFIG_CM_TCRAM
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/* disable TCRAM */
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and r2,r2,#CMMASK_TCRAM_DISABLE
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#endif /* #ifdef CONFIG_CM_TCRAM */
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#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
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defined (CONFIG_CM1136JF_S)
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and r2,r2,#CMMASK_LE
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#endif /* cpu with little endian initialization */
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orr r2,r2,#CMMASK_CMxx6_COMMON
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#endif /* CMxx6 code */
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#endif /* ARM102xxE value */
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/* read CM_INIT */
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mov r0, #CM_BASE
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ldr r1, [r0, #OS_INIT]
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/* check against desired bit setting */
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and r3,r1,r2
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cmp r3,r2
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beq init_reg_OK
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/* lock for change */
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mov r3, #CMVAL_LOCK1
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add r3,r3,#CMVAL_LOCK2
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str r3, [r0, #OS_LOCK]
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/* set desired value */
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orr r1,r1,r2
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/* write & relock CM_INIT */
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str r1, [r0, #OS_INIT]
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mov r1, #CMVAL_UNLOCK
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str r1, [r0, #OS_LOCK]
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/* soft reset so new values used */
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b reset_cpu
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init_reg_OK:
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#endif /* CONFIG_CM_INIT */
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mov pc, lr
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#ifdef CONFIG_CM_SPD_DETECT
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/* Fast memory is available for the DRAM data
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* - ensure it has been transferred, then summarize the data
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* into a CM register
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*/
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.globl dram_query
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dram_query:
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stmfd r13!,{r4-r6,lr}
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/* set up SDRAM info */
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/* - based on example code from the CM User Guide */
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mov r0, #CM_BASE
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readspdbit:
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ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */
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and r1, r1, #0x20 /* mask SPD bit (5) */
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cmp r1, #0x20 /* test if set */
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bne readspdbit
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setupsdram:
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add r0, r0, #OS_SPD /* address the copy of the SDP data */
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ldrb r1, [r0, #3] /* number of row address lines */
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ldrb r2, [r0, #4] /* number of column address lines */
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ldrb r3, [r0, #5] /* number of banks */
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ldrb r4, [r0, #31] /* module bank density */
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mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */
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mov r5, r5, ASL#2 /* size in MB */
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mov r0, #CM_BASE /* reload for later code */
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cmp r5, #0x10 /* is it 16MB? */
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bne not16
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mov r6, #0x2 /* store size and CAS latency of 2 */
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b writesize
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not16:
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cmp r5, #0x20 /* is it 32MB? */
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bne not32
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mov r6, #0x6
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b writesize
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not32:
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cmp r5, #0x40 /* is it 64MB? */
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bne not64
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mov r6, #0xa
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b writesize
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not64:
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cmp r5, #0x80 /* is it 128MB? */
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bne not128
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mov r6, #0xe
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b writesize
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not128:
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/* if it is none of these sizes then it is either 256MB, or
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* there is no SDRAM fitted so default to 256MB
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*/
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mov r6, #0x12
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writesize:
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mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */
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orr r2, r1, r2, ASL#12 /* OR in column address lines */
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orr r3, r2, r3, ASL#16 /* OR in number of banks */
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orr r6, r6, r3 /* OR in size and CAS latency */
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str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */
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#endif /* #ifdef CONFIG_CM_SPD_DETECT */
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ldmfd r13!,{r4-r6,pc} /* back to caller */
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#ifdef CONFIG_CM_REMAP
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/* CM remap bit is operational
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* - use it to map writeable memory at 0x00000000, in place of flash
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*/
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.globl cm_remap
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cm_remap:
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stmfd r13!,{r4-r10,lr}
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mov r0, #CM_BASE
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ldr r1, [r0, #OS_CTRL]
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orr r1, r1, #CMMASK_REMAP /* set remap and led bits */
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str r1, [r0, #OS_CTRL]
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/* Now 0x00000000 is writeable, replace the vectors */
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ldr r0, =_start /* r0 <- start of vectors */
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ldr r2, =_armboot_start /* r2 <- past vectors */
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sub r1,r1,r1 /* destination 0x00000000 */
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copy_vec:
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ldmia r0!, {r3-r10} /* copy from source address [r0] */
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stmia r1!, {r3-r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end address [r2] */
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ble copy_vec
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ldmfd r13!,{r4-r10,pc} /* back to caller */
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#endif /* #ifdef CONFIG_CM_REMAP */
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