upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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146 lines
4.0 KiB
146 lines
4.0 KiB
/*
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* DDR Configuration for AM33xx devices.
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/cpu.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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/**
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* Base address for EMIF instances
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*/
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static struct emif_reg_struct *emif_reg[2] = {
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(struct emif_reg_struct *)EMIF4_0_CFG_BASE,
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(struct emif_reg_struct *)EMIF4_1_CFG_BASE};
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/**
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* Base addresses for DDR PHY cmd/data regs
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*/
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static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
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(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
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(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
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static struct ddr_data_regs *ddr_data_reg[2] = {
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(struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
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(struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
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/**
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* Base address for ddr io control instances
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*/
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static struct ddr_cmdtctrl *ioctrl_reg = {
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(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
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/**
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* Configure SDRAM
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*/
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void config_sdram(const struct emif_regs *regs, int nr)
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{
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if (regs->zq_config) {
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/*
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* A value of 0x2800 for the REF CTRL will give us
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* about 570us for a delay, which will be long enough
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* to configure things.
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*/
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writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
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writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
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writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
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writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
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writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
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writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
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}
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writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
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writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
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writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
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}
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/**
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* Set SDRAM timings
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*/
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void set_sdram_timings(const struct emif_regs *regs, int nr)
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{
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writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
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writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
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writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
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writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
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writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
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writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
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}
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/**
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* Configure DDR PHY
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*/
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void config_ddr_phy(const struct emif_regs *regs, int nr)
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{
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writel(regs->emif_ddr_phy_ctlr_1,
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&emif_reg[nr]->emif_ddr_phy_ctrl_1);
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writel(regs->emif_ddr_phy_ctlr_1,
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&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
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}
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/**
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* Configure DDR CMD control registers
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*/
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void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
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{
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if (!cmd)
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return;
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writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
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writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
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writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
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writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
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writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
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writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
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}
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/**
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* Configure DDR DATA registers
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*/
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void config_ddr_data(const struct ddr_data *data, int nr)
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{
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int i;
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if (!data)
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return;
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for (i = 0; i < DDR_DATA_REGS_NR; i++) {
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writel(data->datardsratio0,
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&(ddr_data_reg[nr]+i)->dt0rdsratio0);
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writel(data->datawdsratio0,
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&(ddr_data_reg[nr]+i)->dt0wdsratio0);
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writel(data->datawiratio0,
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&(ddr_data_reg[nr]+i)->dt0wiratio0);
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writel(data->datagiratio0,
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&(ddr_data_reg[nr]+i)->dt0giratio0);
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writel(data->datafwsratio0,
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&(ddr_data_reg[nr]+i)->dt0fwsratio0);
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writel(data->datawrsratio0,
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&(ddr_data_reg[nr]+i)->dt0wrsratio0);
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}
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}
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void config_io_ctrl(const struct ctrl_ioregs *ioregs)
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{
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if (!ioregs)
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return;
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writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
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writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
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writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
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writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
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writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
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#ifdef CONFIG_AM43XX
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writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
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writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
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writel(ioregs->emif_sdram_config_ext,
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&ioctrl_reg->emif_sdram_config_ext);
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#endif
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}
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